Sumio Fukai

A neuron MOS variable logic circuit with the simplified circuit structure

A simple design of a variable logic circuit using neuron MOS transistors is proposed in this paper. The proposed circuit can be constructed with two-stage neuron MOS inverters. The circuit structure is simplified, and the circuit size can also be miniaturized. The validity of the proposed circuit is confirmed through HSPICE simulation and chip fabrication.

Measurement Test of Phase Difference in a High Tc Superconducting Magnet

An excitation test of an experimental superconducting magnet constructed using a high Tc superconductive wire (HTSW) was carried out. From the observation of the voltage and the current waveforms in the superconducting magnet, it was confirmed that the phase difference considerably approximated 90deg. Moreover, the phase difference in the experimental superconducting magnet was measured using the proposed electronic circuit. As a result, it was clarified that its proposed electronic circuit for phase difference measurement had relatively high accuracy

Study on generation of harmonic voltage using synchronous machine with d-axis and q-axis harmonic field windings - part 2

We investigated the harmonic voltages generated by a synchronous machine adding d- and q-axis harmonic field windings to reduce the harmonics in a power line. First, electronic circuits such as a frequency multiplier, band-pass filter, and phase shifter were newly designed and made to carry out the experiment. Next, an experimental circuit, for which an AC voltage of frequency 6f synchronized to the power line voltage of frequency f could be obtained, was constructed to examine the generation of harmonic voltage in more detail. Finally, an experiment involving the generation of harmonic voltage was performed using an experimental synchronous generator with harmonic windings in the d- and q-axis. In this paper, the experimental results on the generation of harmonic voltage by the synchronous machine are presented.

Designing of a neuron MOS current mirror with a transimpedance amplifier

In this paper, we proposed a neuron MOS current mirror with a transimpedance amplifier. A conventional circuit is composed of a voltage amplifier and resistances. However, the resistance voltage drop makes operating range narrow. A proposed circuit is composed of a transimpedance amplifier. And the proposed circuit has high current copy accuracy and wide operating range. The proposed circuit is designed by using the device parameter of the standard CMOS 1.2 mum process. The performance of the proposed circuit is evaluated by HSPICE simulation. Simulation results show that the proposed circuit has better current copy accuracy and lower voltage operation. And the circuit saturation region Vout is 0.4[V] and over.

Buffer with Neuron MOSFETs for class-G headphone driver

A buffer with Neuron MOSFETs is proposed to simplify a Class-G amplifier. For high efficiency and high fidelity, general Class-G amplifier switches high and low supply voltages depending on an input-signal. Therefore, general Class-G amplifier consists of Class-AB and Class-B buffers. This paper proposed that Class-G amplifier could be high efficiency and high fidelity without Class-B buffer by using Neuron MOSFETs. The performance of the proposed Class-G amplifier with Neuron MOSFETs is evaluated by Spectre using ROHM 0.18μm CMOS device parameters.

A high output-swing current mirror with neuron MOSFETs in standard CMOS technology

For low-voltage analog circuits, output-swing of a current mirror is important factor. This paper describes the current mirror with neuron MOSFETs (νCM). The νCM has negative feedback constructed from a transimpedance amplifier (TIA) to reduce an error current. The TIA monitors an error current of the νCM, and the TIA corrects an output current of the νCM in a low operating voltage. Implemented in TSMC 0.35μm standard CMOS technology, the νCM achieves a minimum output voltage of 30mV and the error current rate of 1%, a quiescent power of 74μW while occupying an area of 0.024mm2.

A study of automatic measuring circuit suitable for very small phase difference measurement

In this paper, we propose an automatic measuring circuit suitable for the simplified very small phase difference measurement circuit. The proposed circuit consists of a J-FET, envelop detection circuit and microcontroller (Arduino). The experiment of automatic phase difference measurement is performed using proposed circuit and automatic amplitude adjustment algorithm. As a result, the error rate of phase difference measurement is ±0.03% or less at phase difference up to about 0.64 deg.

Multiple-output neuron MOS current mirror with bias circuit suitable for Digital-to-Analog converter

This paper proposes a multiple-output neuron MOS current mirror with bias circuit suitable for a 14-bit current-steering D/A converter. Area of the D/A converter is decreased by sharing a floating-gate of a neuron MOSFET. A novel bias circuit is needed for sharing the floating-gate. The multiple-output neuron MOS current mirror with bias circuit reduces the total gate area to 1/811 the multiple-output neuron MOS current mirror without bias circuit. The performance of the proposed circuit is evaluated by HSPICE simulation with On-Semiconductor 1.2μm CMOS device parameters. Simulation results show that the proposed circuit realizes saturation region in V out >; 0.2[V], the current copy accuracy is 99.99863%.

Multiple-valued SRAM with FG-MOSFETs

In this paper, we propose a novel multiple-valued SRAM cell composed of floating gate-MOSFETs (FG-MOSFET). The proposed circuit can memorize multiple signals per memory cell, and effective to use it as SRAM cell with a multiple-valued logic system. The proposed circuit is the multiple-valued SRAM cell that can be composed of a little number of elements by using the FG-MOS level shift circuit. Securing the noise margin is a very important problem because a multiple-valued logical system is weaker to the noise than a binary logical system. The proposed circuit can secure a steady noise margin in low power-supply voltage. And it is low power consumption. In verification using HSPICE simulations, each stable state can secure a steady noise margin of 0.7V or more for the four-valued SRAM cell with 3V power-supply. The proposed circuit is designed by using the device parameter of the standard CMOS 1.2mum process. The performance of multiple-valued SRAM is evaluated by HSPICE simulation