Sun-Yen Tan

Non-XOR approach for low-cost bit-parallel polynomial basis multiplier over GF(2 m )

Finite field arithmetic has been widely used in many cryptosystems, particularly in the elliptic curve cryptosystem (ECC) and the advanced encryption standard (AES) as a method for speeding up their encryption/decryption processes. Low-cost design for finite field arithmetic is more attractive for various mobile applications. It is a factor that a large number of Exclusive OR (XOR) gates have been used in the arithmetic operations under the traditional finite field arithmetic implementation. Thus, the cost of the traditional finite field arithmetic cannot be effectively lowered, because a typical XOR gate design consists of 12 transistors. To address this, a novel non-XOR approach consisting of eight transistors, for realising low-cost polynomial basis (PB) multiplier over GF(2 m ) was developed in this study. The authors proposed that non-XOR architecture for bit-parallel PB multiplier uses the multiplexer function instead of the traditional XOR function in its design. Based on the proposed non-XOR methodology, three popular low-cost irreducible polynomials - trinomial, pentanomial and all-one-polynomial - are proposed and designed in this study. The results indicate that the proposed non-XOR architecture can reduce space complexity by 22-, compared with that of the traditional design.

A novel design to prevent crosstalk

Modern electronics products must have improved characteristics, including high-speed, high-density, and lower-voltage operations. With such designs, a poor PCB (printed circuit board) layout in the signal integrity (SI) system is affected by the noise and becomes unstable. Crosstalk is a major noise that interferes with SI. Generally, a guard trace is added between victim and the other the aggressor to prevent crosstalk. Two grounded vias are added between two ends of this guard trace, respectively, for reducing crosstalk. With the working frequency being higher and higher, crosstalk interferes more and more serious. Even, this guard trace will be as one noise source to affect victim. In this paper, we present the effects of a guard trace with the optimal number of grounded vias that gives the maximum efficiency for preventing crosstalk in parallel double micro-strip lines in a high-speed PCB layout. In comparison with a guard trace with two terminal grounded vias, our swing of the near-end crosstalk is its 37%, and our swing of far-end crosstalk is its 45%.

A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE ¤

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.