Suna Kim

A CMOS Wideband Highly Linear Low-Noise Amplifier for Digital TV Applications

This paper presents a highly linear wideband differential low-noise amplifier (LNA) for digital TV applications. The proposed LNA is a modified version of the wideband LNA reported by Bruccoleri in 2004. In order to increase the linearity of Bruccoleri s LNA, the Volterra series is adopted to identify the nonlinear components and the noise-cancelling circuit is modified to eliminate the whole nonlinear components. Implemented in 0.13-μm CMOS technology, the proposed wideband LNA has a gain of 12.4 dB and a noise figure of 1.6 dB, as determined from measurements, while drawing 18.45 mA from a 1.2-V supply. The proposed LNA has an IIP3 of 16.6 dBm with 6-MHz frequency offset at 100 MHz, far exceeding the values of existing wideband LNAs.

MOSFET Characteristics for Terahertz Detector Application From On-Wafer Measurement

In this paper, we report on MOSFET characteristics for terahertz (THz) detector application from precise on-wafer measurement, and the results are compared with theories and SPICE simulations. Techniques for precise measurement using a vector network analyzer and on-wafer probing and simulation based on the SPICE model are introduced. Several MOSFETs in various channel dimensions are fabricated in 65-nm CMOS technology and measured over gate bias voltage and the operating frequencies of 110, 200, and 300 GHz using the lock-in technique. The behavior of responsivity and noise equivalent power (NEP) depending on the channel width and length of the MOSFET and the frequency are investigated, and trends of the obtained results are in good agreement with the theories and the simulations. The channel width dependence of the responsivity of the MOSFET detector is evaluated and explained for the first time. The results of this work can provide a reliable and useful reference for the design of THz detectors.

A New Resistance Model for a Schottky Barrier Diode in CMOS Including N-well Thickness Effect

A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variale to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a 0.13㎛ CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD.

A CMOS highly linear low-noise amplifier for Digital TV applications

This paper presents a highly linear low-noise amplifier (LNA) for Digital TV applications. By including a second-order nonlinear cancelling transistor to the noise cancelling circuit, the proposed LNA achieves high IIP3 which is immune to the offset frequency of two tone signals. The proposed LNA is implemented as a differential architecture in 0.13 μm CMOS technology, and measurements show +17.8 dBm, 12.4 dB and 1.6 dB of IIP3, gain and NF, respectively, while drawing 18.45 mA from 1.2 V.

A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS

An ultra-low power and wide tuning range LC-VCO is presented, where the performances are improved by identifying and avoiding the Q-factor degradation factors in the LC-tank. By the positioning analysis and adoption of MIM capacitor arrays along with minimum size varactors, the proposed VCO with a high-Q inductor, implemented in a 65-nm CMOS technology, operates from 2.35GHz to 2.64GHz (11.7% tuning) with phase noise of -132.92 dBc/Hz at 1MHz offset while dissipating only 72μW from a 0.6-V supply. The FoM of the proposed VCO is 212dBc/Hz and the widest tuning range is shown in the high-Q oscillators.