Sundararaman Gopalan

Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric

Electrical and reliability properties of ultrathin HfO/sub 2/ have been investigated. Pt electroded MOS capacitors with HfO/sub 2/ gate dielectric (physical thickness /spl sim/45-135 /spl Aring/ and equivalent oxide thickness /spl sim/13.5-25 /spl Aring/) were fabricated. HfO/sub 2/ was deposited using reactive sputtering of a Hf target with O/sub 2/ modulation technique. The leakage current of the 45 /spl Aring/ HfO/sub 2/ sample was about 1/spl times/10/sup -4/ A/cm/sup 2/ at +1.0 V with a breakdown field /spl sim/8.5 MV/cm. Hysteresis was <100 mV after 500/spl deg/C annealing in N/sub 2/ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO/sub 2/ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V/sub DD/=2.0 V.

High-performance TaN/HfSiON/Si metal-oxide-semiconductor structures prepared by NH3 post-deposition anneal

Electrical and chemical characteristics of metal-oxide semiconductor field-effect transistors (MOSFETs) prepared by low-thermal-budget (∼600 °C) NH3 post-deposition annealing of HfSiON gate dielectric have been investigated. Compared to control Hf-silicate, HfSiON showed excellent thickness scalability, low leakage current density (J), and superior thermal stability. With proper annealing-time optimization, effective oxide thickness as low as 9.2 A with J<100 mA/cm2 at gate voltage Vg=−1.5 V has been achieved. C–V hysteresis of HfSiON MOSFET was found to be small (<20 mV). Unlike NH3 surface nitridation (NH3 pre-treatment prior to Hf-silicate deposition), no degradation in Gm (transconductance), Id–Vg (drain current–gate voltage), or Id–Vd (drain current–drain voltage) characteristics has been observed.

Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing

The surface electron mobility of HfO/sub 2/ NMOSFETs with a polysilicon gate electrode was studied in terms of the effects of high-temperature forming gas (FG) annealing. The high-temperature FG annealing significantly improved the drive current or the surface electron mobility of the NMOSFETs. Improvements were also observed in the subthreshold swings and the C-V characteristics, indicating a reduction in interfacial state density (D/sub it/). The D/sub it/ reduction was quantitatively confirmed by charge pumping current measurements. The mobility enhancement was achieved without degrading the equivalent oxide thickness (EOT) or gate leakage current. Different surface preparations, such as NH/sub 3/ or NO annealing, were explored to examine their effects on the NMOSFET performance. Mobility enhancement due to high-temperature FG annealing was also observed on these samples. Whereas NH/sub 3/ surface nitridation was effective in scaling EOT, the NO-annealed sample exhibited the highest mobility. Similar improvements were also observed on HfO/sub 2/ PMOSFETs, in terms of subthreshold swings, drive current, and surface hole mobility.

Structural and electrical properties of HfO 2 with top nitrogen incorporated layer

A novel technique to control the nitrogen profile in HfO/sub 2/ gate dielectric was developed using a reactive sputtering method. The incorporation of nitrogen in the upper layer of HfO/sub 2/ was achieved by sputter depositing a thin Hf/sub x/N/sub y/ layer on HfO/sub 2/, followed by reoxidation. This technique resulted in an improved output characteristics compared to the control sample. Leakage current density was significantly reduced by two orders of magnitude. The thermal stability in terms of structural and electrical properties was also enhanced, indicating that the nitrogen-doped process is effective in preventing oxygen diffusion through HfO/sub 2/. Boron penetration immunity was also improved by nitrogen-incorporation. It is concluded that the nitrogen-incorporation process is a promising technique to obtain high-k dielectric with thin equivalent oxide thickness and good interfacial quality.

Evaluation of silicon surface nitridation effects on ultra-thin ZrO2 gate dielectrics

The effects of silicon surface nitridation on metal–oxide–semiconductor capacitors with zirconium oxide (ZrO2) gate dielectrics were investigated. Surface nitridation was introduced via ammonia (NH3) annealing prior to ZrO2 sputter-deposition, and tantalum nitride (TaN) was used for the gate electrode. It was found that capacitors with the nitridation had thinner equivalent oxide thickness (∼8.7 A), comparable leakage current, and slightly increased capacitance–voltage hysteresis as compared to samples without nitridation. Additionally, transmission electron microscopy pictures revealed that nitrided samples had a thicker interfacial layer (IL), which had a higher dielectric constant than that of the non-nitrided IL.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 /spl Aring/-12 /spl Aring/)

MOSFETs with equivalent oxide thickness of 8-12 /spl Aring/ have been demonstrated by using high-K gate dielectric thin films (HfO/sub 2/) and TaN gate electrode. Both self-aligned (higher thermal budget process) and non-self-aligned process (low thermal budget as in the replacement gate process) were used and compared. Excellent electrical characteristics (e.g. S/spl sim/68 mV/dec) and reliability characteristics (e.g. high E/sub BD/, low charge trapping and SILC) were also obtained.

Electrical and physical characteristics of ultrathin hafnium silicate films with polycrystalline silicon and TaN gates

Metal-oxide-semiconductor transistors of ultrathin hafnium silicate films (equivalent oxide thickness (EOT) of 12.5–14 A) with polycrystalline silicon and metal (TaN) gates have been demonstrated. Well-behaved transistor characteristics and EOT stability of Hf silicate with n+ polysilicon indicates good compatibility with polysilicon gate process without use of barrier layer. Transmission electron microscopy analysis indicates that the films have no top interfacial layer with both TaN and polysilicon gates. The films also remain amorphous and show no indication of phase separation even after a 950 °C dopant activation anneal. Hf silicate films also show excellent transistor characteristics with TaN gate. NH3 pretreatment results in degraded transistor characteristics for TaN and poly gate samples. Good capacitance–voltage characteristics and negligible hysteresis (<10 mV) was observed in the capacitors after a 1000 °C activation indicating good electrical stability at high temperatures and minimal charge ...

High-quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs with TaN electrode and nitridation surface preparation

A surface preparation technique using an NH/sub 3/ anneal has been investigated to reduce interface reaction and consequently the equivalent oxide thickness (EOT) of hafnium oxide for alternative gate dielectric applications. MOSCAPs and MOSFETs were fabricated on the NH/sub 3/ nitrided substrates with HfO/sub 2/ dielectric and TaN gate electrode. Using this nitridation technique, EOT of as thin as 7.1 /spl Aring/ with 10/sup -2/ A/cm/sup 2/ at -1.5 V was obtained. Furthermore, excellent device characteristics and reasonable reliability have been achieved.

Novel nitrogen profile engineering for improved TaN/HfO/sub 2//Si MOSFET performance

A novel technique to tailor the nitrogen profile in HfO/sub 2/ gate dielectric has been developed. Nitrogen was incorporated in the upper layer of HfO/sub 2/ using a reactive sputtering method, followed by a reoxidation anneal. The resulting dielectrics showed good thermal stability, boron penetration suppression, low interfacial trap density, plus lower hysteresis and improved MOSFET characteristics, in comparison to both non-nitrided and bottom nitrided (via Si-surface nitridation with NH/sub 3/) devices.