Sung-man Kim

P‐24: Low Power a‐Si:H TFT Gate Driver Circuit Employing Negative Turn Off Biasing

New a-Si:H TFT gate driver circuit (ASG) for low power consumption is proposed and fabricated. For the first time, the proposed ASG can set TFT turn off voltage to the negative voltage rather than zero voltage that the conventional one uses, therefore, TFT leakage current can dramatically be reduced by 1/100. The size of TFT in new ASG, which discharges the leakage current, can be reduced so that the power consumption of new ASG is 43% of the conventional one.

A Study on Contact Resistance Failure Between Al-Ti-TiN Multi-Layer and W-Via Caused by Hillock Formation

We studied how hillock in Al film increases the contact resistance (RC) between bottom-side metal stacked (Al-Ti-TiN) and upper-side W-via-plugs in the backend-structure of the semiconductor. The general structure is the via-etch-stop-on-TiN (VEST), otherwise the via-etch-stop-on-Al (VESA) was observed on the hillocks. After metal etching, the sputtering as well as the deposition (DEPO) is conducted for IMD gap-filling in the FSG process. The sputtering makes the TiN surface with the hillock cliffy and the TiN cannot take a role of the Al capping layer from via etching. We found that the oxidation of Al below recessed TiN is the main cause of the high RC. To prevent the hillock, the metal DEPO temperature is increased and the temperature of metal-etch-mask-oxide is decreased. Furthermore, the thickness of TiN increased for relieving clipping from the FSG process. Thanks to those actions, we could completely overcome the high RC issue caused by the hillock.