Sung-ryoul Bae

Advanced 0.13um smart power technology from 7V to 70V

This paper presents BCD process integrating 7V to 70V power devices on 0.13um CMOS platform for various power management applications. BJT, Zener diode and Schottky diode are available and non-volatile memory is embedded as well. LDMOS shows best-in-class specific Ron (R_SP) vs. BV_DSS characteristics (i.e., 70V NMOS has R_SP of 69mΩ-mm² with BV_DSS of 89V). Modular process scheme is used for flexibility to various requirements of applications.

Effects of H/sub 2/ annealing and polysilicon emitter structure on H/sub FE/ of n-p-n bipolar junction transistors

This paper presents the effects of H/sub 2/ annealing and polysilicon emitter structures on H/sub FE/ characteristics of n-p-n bipolar junction transistors. The increase of the number of H/sub 2/ annealing steps results in the device performance (H/sub FE//spl times/V/sub A/) improvement by 27.8%, due to the formation of H-Si dangling bonds, which allow the decrease of the base current. In addition, the bilayer of undoped polysilicon deposition/ion implantation and in situ doped polysilicon in the ploy emitters greatly improve the level of H/sub FE/ reliability and 1/f noise characteristic. The experimental results of H-Si dangling bond property at the polysilicon grain boundaries and polysilicon interface with the H/sub 2/ annealing steps in n-p-n bipolar junction transistor formulation will be also presented.