Sung-Sun Choi

A 2.4 /5.2-GHz Dual Band CMOS VCO using Balanced Frequency Doubler with Gate Bias Matching Network

This paper presents the design and measurement of a 2.4/5.2-㎓ dual band VCO with a balanced frequency doubler in 0.18 ㎛ CMOS process. The topology of a 2.4 ㎓ VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 ㎓ VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 ㎓ and 5.2 ㎓ VCOs are -12 ㏈m and -13 ㏈m, respectively, the doubled VCO has fundamental harmonic suppression of -25 ㏈. The measured phase noises at 5 ㎒ frequency offset are -123 ㏈c /㎐ from 2.6 ㎓ and -118 ㏈c /㎐ from 5.1 ㎓. The total size of the dual band VCO is 1.0 ㎜×0.9 ㎜ including pads.

Ka-band hybrid phase shifter for analog phase shift range extension using 0.13-μm CMOS technology

This paper presents a new concept of the phase shifter design called a hybrid phase shifter. The proposed hybrid phase shifter consists of an analog-type active phase shifter and a digital-type passive phase shifter. To verify the idea the circuit is designed using 0.13-μm RF CMOS technology at 22–26-GHz UWB frequency band. The hybrid phase shifter has the continuous phase shift range up to 25.40, which is able to cover almost two times of the designed analog or digital phase shifter range. The gain drift of about −2.0 dB to 0.7 dB at 24-GHz is observed during phase shift. The simulation results confirm that the proposed hybrid phase shifter can be a good candidate as one of the phase shifter for the implementation in active phased array or multi-antenna beamforming system.