Sung-Wook Moon

Analysis and Estimation on EMI Effects in AP-DRAM Interface for a Mobile Platform

Electromagnetic Interference (EMI) is an increasingly important factor in determining whole-system performance of a mobile system. This is driven by size reduction of the mobile platform and the ever-increasing density of electronic components. In this work, we suggest an analysis approach for EMI effects in the interface between an application processor (AP) and dynamic random-access memory (DRAM) by using an I/O driver model including power delivery network (PDN) effects. By applying this approach, the EMI effect by the AP-DRAM interface is able to be accurately estimated when its operating frequency is shifted up/downward depending on the scheme of mobile operations. The EMI effect in the AP-DRAM interface can be characterized by the (1) on-chip metal layout and package layout of the I/O PDN, (2) inserted decoupling capacitance of the I/O PDN, (3) I/O driver properties that define the rising/falling time of signals, and (4) channel properties including crosstalk between adjacent lanes and their frequency response at data transfer. In a time-domain simulation, the extracted I/O driver model was used with extracted AP and memory package models, a channel model, and an interposer. The simulation was carried out by varying input stimulus depending on a bit density ratio, bit length, and a test pattern. As a result, a wide range of spectrum generated by the AP-DRAM interface up to 6 GHz was calculated. The bandwidth of data queue (DQ) signals at the interposer was found to be around 170MHz with multiple harmonics of the fundamental 1.6GHz frequency. In comparison to the measurement, the difference in bandwidth was found to be less than 10MHz and the voltage difference at the harmonics was found to be less than 10dB. Consequently, we proposed an analysis and estimation approach for EMI effects in an AP-DRAM interface which affects the degradation of communication performance in a compact mobile platform and successfully demonstrated its applications for predicting EMI effect in the communication band of interest.

An accurate on-chip design estimation for mitigating EMI effects in a large-scale integration chip

Inside an electronic product with high-speed interfaces, a lot of technological effort is required for neutralizing mutual electromagnetic interference (EMI) between adjacent electronic components. Thus, it is necessary to adopt an EMI-aware design to maintain high-performance features by avoiding possible EMI causes in a large-scale integration (LSI) chip. In this work, we analyzed IC-level EMI causes for improving on-chip EMI perspectives by characterizing composing channel impedance with a view to the whole system. A test channel for characterizing system-level impedance properties consists of power/ground nets of on-chip metal layers, a chip-on film (CoF), and a printed circuit board (PCB). Specifically, we compared two test samples with different features. One (sample 1) has a 0.8nF on-chip decoupling capacitor, only horizontal Vdd-Vss pairing layout for power interconnects, and 0.2T clock shift scheme from data edge position. The other (sample 2) has a 1.5nF on-chip decoupling capacitor, both vertical and horizontal Vdd-Vss pairing layout for confining an EM field, and 0.5T clock shift scheme for frequency spreading effect. Using simulation results and frequency domain analysis, the impedance was found to be 1.3 Ohm to 0.9 Ohm at a specific noise frequency of interest (132MHz) as the decoupling capacitance increases from 0.8 nF to 1.5nF. In comparison, the performance of EMI properties in sample 2 was found to be improved by 6.0dB when compared to sample1. Specifically, this improvement turned out to be affected by 3.2dB due to increasing on-chip decoupling capacitance of 0.7dB due to a shielding effect on the power/ground interconnect layout of an added metal layer and 1.6dB due to changing the scheme of a clock timing transition. In the simulation-based estimation, this 5.5dB improvement was demonstrated to agree with the near-field measurement with a 6.0dB improvement. Consequently, our approach to analyze on-chip EMI effects is helpful to understand complex electromagnetic behaviors in an LSI chip and it is also expected to be applicable in suppressing complex EMI causes for leveraging on-chip EMI performance.

An early-EMI analysis method for the LPDDR interface

In this paper, an accurate noise level estimation technique in the design stage for LPDDR system is presented. In order to predict the system performance, the equivalent circuit based simulation model and the input parameter range for the sweep simulation is required. The package and board are modeled by using RLC equivalent circuits. The input parameter range is determined by investigating the characteristics of the existing products. The noise level of the LPDDR system in the mobile platform can be estimated by using equivalent circuit model and input parameters. It is shown that noise level at the input pad of the receiver using the proposed method has a good agreement with S-Parameter based model within less than 8dB.

A novel approach for ESD-immunity analysis using channel transfer impedance on the power delivery network of a large-scale integration chip

In this work, we proposed a novel approach for electrostatic discharge (ESD) noise stress analysis using transfer impedance analysis in a platform for a large-scale integration chip. In the electronic industry an ESD test is widely taken to evaluate the noise immunity of a designed electronic device. In this ESD test, critical hardware damage or functional problems may occur due to temporary electrical disturbances produced by applying an external electrical shock. By manipulating the transfer-impedance difference from a noise-induced point to power/ground points of an IC, the influence of an induced ESD noise that could significantly affect the ICs performance was analyzed. The ESD noise stress affects supply voltage to become unstable in a power delivery network (PDN) and adversely affects analog/digital circuit operations during data processing. The impedance differences in the PDN produces supply voltage instability in a designed chip. Thus, by analyzing the transfer impedance from the PCB to the power nets of a time-controller IC, the variation of supply voltage due to external ESD noise can be estimated. In order to separate noise-to-power and noise-to-ground paths on a PCB, an additional ground layer, which exists only in simulation, was used for estimating temporal voltage fluctuation due to impedance imbalance between the noise-to-power and the noise-to-ground paths. In comparison, the proposed approach was demonstrated to agree with the measurement up to 500 MHz. This estimation result indicated that the simulation approach on ESD noise immunity using transfer impedance is useful to predict the influence of electrical stress to a designed IC on a PCB. The estimation approach on ESD noise impact is expected to be applicable for the PDN design of a PCB/IC to improve its ESD noise immunity prior to its implementation.