Sunggu Lee

Design and implementation of a private and public key crypto processor and its application to a security system

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used for various security applications such as storage devices, embedded systems, network routers, security gateways using IPSec and SSL protocol, etc. The crypto processor consists of a 32-bit RISC processor block and coprocessor blocks dedicated to the AES, KASUMI, SEED, triple-DES private key crypto algorithms and ECC and RSA public key crypto algorithm. The dedicated coprocessor block permits fast execution of encryption, decryption, and key scheduling operations. The 32-bit RISC processor block can be used to execute various crypto algorithms such as Hash and other application programs such as user authentication and IC card interface. The crypto processor has been designed and implemented using an FPGA, and some parts of crypto algorithms has been fabricated as a single VLSI chip using 0.5 /spl mu/m CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed.

Power management of hybrid DRAM/PRAM-based main memory

Hybrid main memory consisting of DRAM and non-volatile memory is attractive since the non-volatile memory can give the advantage of low standby power while DRAM provides high performance and better active power. In this work, we address the power management of such a hybrid main memory consisting of DRAM and phase-change RAM (PRAM). In order to reduce DRAM refresh energy which occupies a significant portion of total memory energy, we present a runtime-adaptive method of DRAM decay. In addition, we present two methods, DRAM bypass and dirty data keeping, for further reduction in refresh energy and memory access latency, respectively. The experiments show that by reducing DRAM refreshes, we can obtain 23.5%∼94.7% reduction in the energy consumption with negligible performance overhead compared with the conventional DRAM-only main memory.

Probabilistic diagnosis of multiprocessor systems

This paper critically surveys methods for the automated probabilistic diagnosis of large multiprocessor systems. In recent years, much of the work on system-level diagnosis has focused on probabilistic methods, which can diagnose intermittently faulty processing nodes and can be applied in general situations on general interconnection networks. The theory behind the probabilistic diagnosis methods is explained, and the various diagnosis algorithms are described in simple terms with the aid of a running example. The diagnosis methods are compared and analyzed, and a chart is produced, showing the comparative advantages of the various diagnosis algorithms on the basis of several factors important to the probabilistic diagnosis.

Interleaved all-to-all reliable broadcast on meshes and hypercubes

All-to-all (ATA) reliable broadcast is the problem of reliably distributing information from every node to every other node in point-to-point interconnection networks. A good solution to this problem is essential for clock synchronization, distributed agreement, etc. We propose a novel solution in which the reliable broadcasts from individual nodes are interleaved in such a manner that no two packets contend for the same link at any given time-this type of method is particularly suited for systems which use virtual cut-through or wormhole routing for fast communication between nodes. Our solution, called the IHC Algorithm, can be used on a large class of regular interconnection networks including regular meshes and hypercubes. By adjusting a parameter /spl eta/ referred to as the interleaving distance, we can flexibly decrease the link utilization of the IHC algorithm (for normal traffic) at the expense of an increase in the time required for ATA reliable broadcast. We compare the IHC algorithm to several other possible virtual cut-through solutions and a store-and-forward solution. The IHC algorithm with the minimum value of /spl eta/ is shown to be optimal in minimizing the execution time of ATA reliable broadcast when used in a dedicated mode (with no other network traffic). >

A real-time communication method for wormhole switching networks

In this paper we propose a real-time communication scheme that can be used in general point-to-point real-time multicomputer systems with wormhole switching. Real-time communication should satisfy the two requirements of predictability and priority handling. Since traditional wormhole switching does not support priority handling which is essential in real-time computing, flit-level preemption is adopted in our wormhole switching. Also, we develop an algorithm to determine the message transmission delay upper bound to predict worst-case message delay. Simulation results show that the delay upper bounds calculated using the proposed algorithm are very close to actual average message transmission delays for messages with high priorities.

Data Dissemination for Wireless Sensor Networks

Due to the special characteristics (limited battery power, limited computing capability, low bandwidth, need to collect sensor data from multiple fixed-location source nodes to a sink node that may be mobile, etc.) of wireless sensor networks, routing algorithms designed for general mobile ad hoc networks may not be directly applicable to wireless sensor networks. In one possible routing scheme for wireless sensor networks, each node maintains up-to-date hop-distances and next-hop nodes to the mobile sink node (or multiple mobile sink nodes). However, this type of method may require too much control overhead in order to maintain up-to-date and consistent hop-distances and next-hop nodes for all of the sensor nodes in the network. Therefore, we propose a new low-control-overhead data dissemination scheme, referred to as pseudo-distance data dissemination, for efficiently disseminating data packets from all sensor nodes to mobile sink nodes in a wireless sensor network

Design for test using partial parallel scan

Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one to two orders of magnitude is presented. Theoretical and practical aspects of the design method are discussed. The practical use of the partial parallel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools. >

Real-time wormhole channels

For real-time communication, we must be able to guarantee timely delivery of messages. In recent years, improvements in technology have made possible switch-based local area networks (LANs) and system area networks (SANs) that use wormhole switching, a pipelined switching technique which permits significantly shorter network latencies and higher throughputs than traditional store-and-forward packet switching. This paper proposes a model for real-time communication in such wormhole networks based on the use of real-time wormhole channels, which are simplex virtual circuits in wormhole networks with certain real-time guarantees. A distinguishing feature of our model is that it can be used in existing wormhole networks without any special hardware support. Preliminary delay analysis and properties are shown for the proposed real-time wormhole channel model. A practical quadratic time complexity algorithm is shown for determining the feasibility of a set of wormhole channels. Finally, as an example of the utility of our model, actual parameter values obtained from experiments on a Myrinet switch-based network are used to determine if real-time guarantees are possible for an example set of real-time traffic streams intermixed with nonreal-time traffic.

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).

Bloom filter-based dynamic wear leveling for phase-change RAM

Phase Change RAM (PCM) is a promising candidate of emerging memory technology to complement or replace existing DRAM and NAND Flash memory. A key drawback of PCMs is limited write endurance. To address this problem, several static wear-leveling methods that change logical to physical address mapping periodically have been proposed. Although these methods have low space overhead, they suffer from unnecessary data migrations thereby failing to exploit the full lifetime potential of PCMs. This paper proposes a new dynamic wear-leveling method that reduces unnecessary data migrations by adopting a hot/cold swapping-based dynamic method. Compared with the conventional hot/cold swapping-based dynamic method, the proposed method requires only a small amount of space overhead by applying Bloom filters to the identification of hot and cold data. We simulate our method using SPEC2000 benchmark traces and compare with previous methods. Simulation results show that the proposed method reduces unnecessary data migrations by 58~92% and extends the memory lifetime by 2.18~2.30 times over previous methods with a negligible area overhead of 0.3%.