Sungyoul Seo

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction

As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.

An Efficient RPCT (Reduced Pin Count Testing) based on Test Data Compression using Burst Clock Controller in 3D-IC

RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the existing DFT(Design for Test) circuitry. The experimental results show that the proposed method can drastically reduce test cost, ATE dependence and testing complexity.

Software-based embedded core test using multi-polynomial for test data reduction

Software-based self-test (SBST) is a self-test where processors and intellectual property (IP) cores test itself using an embedded memory. However, an environment-limited memory size is one of the biggest challenges. In this paper, we present a new SBST solution using multiple polynomials. For reducing the required test data, the polynomials consist of a primitive polynomial and (BM)-algorithm based polynomials and each polynomial generates pseudo random patterns and deterministic patterns respectively. Experimental results show that this SBST method reduces the size of the test program without a reduction of the fault coverage.

A test methodology to screen scan-path failures

It is important to screen scan-path failures because scan-path failures affect product yield even though these are not related to the device functional operations. However, the additional efforts such as diagnosis are required to screen scan-path failures. In this paper, we propose a new test methodology to screen scan-path failures under the Automatic-Test-Pattern-Generation (ATPG) constraints and the multi-capture-clock condition without diagnosis. Experimental results show that the proposed methodology efficiently screens scan-path failures with high test coverage.