Sunil Ashtaputre

A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs

The authors present an automatic layout system for designing large sea-of-gates gate arrays. This tool combines a floorplanning tool with an automatic placement and routing tool. It is designed to handle 250 K-gate arrays with special functional blocks such as RAM and ROM. It provides features for current processing, timing-driven layout, special clock distribution, and power distribution. The tool is currently being tested for designing the industrys most complex sea-of-gates gate arrays

A new faster algorithm for iterative placement improvement

We present a new faster design-style independent iterative placement improvement algorithm. Randomized simulated annealing based algorithms produce good result. But on very large designs, the inherently long run-time makes it prohibitive to use randomized algorithm. On the other hand deterministic improvement methods do not produce as good a result as the simulated annealing based algorithms. Moreover, none of the existing placement improvement techniques addresses the non row-based design style. In this paper, we combine the advantages of both the random and deterministic approach to develop a new faster placement improvement algorithm. Experimental results show that our algorithm performs much better than existing placement improvement algorithm. On some benchmarks, our algorithm is as much as 8/spl times/ faster than that on Domino with a significant reduction in total net length.