Sunil Pandey

Realization of efficient RF energy harvesting circuits employing different matching technique

Power management and charging of batteries for wireless sensors become a problem when using them in the field applications. In this paper, we present RF energy harvesting circuit with three different approaches: resonator, number of multiplier stages and low pass filter (LPF). Resonator provide 30 times improvement in amplitude of input (100 mV) AC signal. In proposed circuit L type network, between input power source and rectifier, works as resonator as well as matching network at resonant frequency. It results in maximum efficiency 79% with 50kO load at -10 dBm input power. We also present the effect of multiplier stages on output voltage and RF to DC conversion efficiency. Optimum efficiency of approximately 80% is achieved with Dickson topology in input power region 0 to 10dBm for 3rd, 5th and 7th stages, respectively. Application of LPF is also introduced with an existing circuit. It provides 140 mV improvement in output voltage with input power -10dBm. It also shows that maximum efficiency 75% and 64% is possible with dielectric constant (er=9) and substrate height (H=0.0004m), for microstrip line of matching circuit at -10 dBm input power with 10 kO load.

A Charge-Plasma-Based Dielectric-Modulated Junctionless TFET for Biosensor Label-Free Detection

To reduce the fabrication complexity and cost of the nanoscale devices, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field-effect transistor (DM-JLTFET) for biosensor label-free detection. The formation of p+ source and n+ drain regions in DM-JLTFET is done by the deposition of platinum (work function = 5.93 eV) and hafnium (work function = 3.9 eV) materials, respectively, over the silicon body. Furthermore, a nanogap cavity embedded within the gate dielectric is created by etching the portion of gate oxide layer toward the source end for sensing biomolecules. For this, the sensing capability of DM-JLTFET has been investigated in terms of variation in dielectric constant, charge density, length, and thickness of the cavity at different bias conditions. Finally, a comparative study between DM-JLTFET and MOSFET biosensor is investigated. The implementation of proposed device and all the simulations have been performed by using ATLAS device simulator.

A highly linear RF mixer using gate-all-around junctionless transistor

ABSTRACT In this paper, we investigate the performance of a radio-frequency (RF) mixer based on single-silicon nanowire gate-all-around (GAA) junctionless field-effect transistor (JLFET). The main novelty in this work is the achievement of high linearity of RF mixer using band-to-band tunnelling phenomenon of GAA-JLFET. Using technology computer-aided design (TCAD) simulations, we extracted the value of unity-gain cut-off frequency of 420 GHz, which shows its potential for circuit applications in the extremely high-frequency regime. The harmonic-balanced simulations in Agilent advanced design system tool with an emphasis on the device-circuit interaction are used to analyse the RF mixer performance, such as output spectrum, 1-dB compression point, and conversion gain in comparison with 32-nm conventional n-metal oxide semiconductor transistor.

A low power and high gain CMOS LNA for UWB applications in 90nm CMOS process

This paper presents a two stage low noise amplifier (LNA) to achieve low power and high gain for 3.1-10.6GHz ultra-wide band (UWB) applications. Its first stage yields exceptionally wideband input matching because of the input impedance Z in = 1 / g m 1 ? 50 ? of the common-gate (CG) input matching transistor. A source degenerated common source (CS) topology with the shunt peaking inductor L d 2 is designed as the second stage to improve the overall gain response. Using a standard 90nm CMOS process, the proposed LNA achieves a gain S21 approximately equal to 20dB, while consuming only 4.33mW power from a 0.6V supply voltage. With the aid of source degenerated inductor, the simulation results show input return loss S 11 < - 10 dB in the frequency range of 3.1-9.7GHz, a noise figure (NF) less than 1.41dB, and the minimum noise figure (NFmin) below 1.034dB in the frequency range of 3.1-10.6GHz. When a two tone test is performed with a frequency spacing of 2MHz, the third order input intercept point (IIP3) of -22dBm is achieved. The other advantages of the proposed LNA are its small group-delay variation and gain variation of ?28ps and ?0.39dB, respectively.

An Efficient RF Energy Harvester with Tuned Matching Circuit

Microstrip line with π matching circuits are very attractive because of high output power and good impedance matching which makes it an alternative over earlier matching circuit. This paper presents an RF energy harvester with microstrip line in series with tuned π-matching circuit that enables efficient power conversion at different RF input power under different load conditions. Matching circuit parameters were optimized for better efficiency. We have focused for specific input power range -15 to 10dBm for 3-stage, 5-stage and 7-stage of energy harvesting circuit. Optimum efficiency of approximately 80% is achieved at input power 0 to 10dBm for higher stages. Effect of load variation also shows that better efficiency is achieved for input power -10 to 10dBm for 3-stage, 5-stage and 7-stage of the harvesting circuit.

Temperature sensitivity analysis of polarity controlled electrically doped hetero-TFET

Polarity controlled (GaAs-Ge) hetero-TFET based on the concept of electrically doped mechanism have shown significant advantages in terms of high Ion current, less ambipolar leakage, less short-channel effects (SCEs) over Si-TFET. However, temperature sensitivity analysis of such a device were not analysed. Therefore, in this work, sensitivity towards temperature variation of recently proposed polarity controlled (GaAs-Ge) hetero tunnel field-effect transistor (H-TFET) is reported. The analog/RF figure-of-merits were considered to analyse the temperature sensitivity analysis of recently reported polarity controlled H-TFET. The simulations were performed using ATLAS technology computer aided design (TCAD) device simulator. We analysed that the Ion/Ioff current of polarity controlled H-TFET decreases with temperature, while, Ioff increases with temperature because of different scattering mechanisms at higher temperature. The variation in gm is 0.2mS for 0.1V gate voltage variation at different temperature in the saturation region. With a small variation in analog/RF FOMs with temperature, we can say that the proposed H-TFET is less sensitive towards temperature variation and can be used for high temperature applications.

Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET

ABSTRACT Ambipolar conduction in tunnel field-effect transistors (TFETs) has been occurred as an inherent issue due to drain-channel tunneling. It makes TFET less efficient and restricts its application in complementary digital circuits. Therefore, this manuscript reports the application of Gaussian doping profile on nanometer regime silicon channel TFETs to completely eliminate the ambipolarity. For this, Gaussian doping is used in the drain region of conventional gate-drain overlap TFET to control the tunneling of electrons from the valence band of channel to the conduction band of drain. As a result, barrier width at the drain/channel junction increases significantly leading to the suppression of an ambipolar current even when higher doping concentration (1 10 cm ) is considered in the drain region. However, significant improvement in terms of RF figure-of-merits such as cut-off frequency (f ), gain bandwidth product (GBW), and gate-to-drain capacitance (C ) is achieved with Gaussian doped gate on drain overlap TFET as compared to its counterpart TFET.

A Charge Plasma Based Dielectric Modulated Heterojunction TFET Based Biosensor for Health-IoT Applications

The health Internet-of-Things (IoTs) applications have motivated to design nanoscale transistor based biosensors. Therefore, in this work, we mainly focus on how emerging transistors such as tunnel field-effect transistor (TFET) can be an alternative beyond-CMOS features for biosensor design and to further increase the low power design strategy to enable it for IoT applications. For this purpose, a charge plasma based dielectrically modulated TFET is proposed in this work, where source region is having SiGe material (with Si and Ge composition equal to 0.5) to improve the ON-state current. The charge plasma concept is employed to make the fabrication process simpler and to avoid the random dopant fluctuations (RDFs) and higher thermal budget. The significant improvement in the sensitivity of the proposed dielectrically modulated junctionless (DMJL) TFET biosensor with different dielectric constant and charge density, and a comparison with conventional MOSFET-based sensor enables its potential application for the Health-IoT applications.

Realization of Junctionless TFET-Based Power Efficient 6T SRAM Memory Cell for Internet of Things Applications

The Internet of Things (IoTs) applications have garnered its interest to realize low-power memory circuit based on emerging nanoscale transistors for its data processing unit. Therefore, in this work, we focussed on tunneling mechanism-based tunnel field-effect transistor (TFET) which can be a suitable option beyond-CMOS devices for designing reliable and efficient memory circuits for its key sensing and data processing unit. However, this work is further extended toward low-power design strategy to meet the essential requirements of IoT applications. For this purpose, a junctionless (JL) TFET based on work-function engineering is reported in this work, where a high-k material (HfO\(_{2}\)) adjacent to the SiO\(_{2}\) toward source side is considered underneath the gate region to improve the ON-current of the proposed device. The main benefits of junctionless architecture is that it reduces the fabrication complexity, high thermal budget, and is free from random dopant fluctuations (RDFs). The significant benefits in terms of hold, read, and write static noise margin (SNM) of JLTFET-based six-transistor (6T) memory cell enables its potential application for IoT memory unit.

Quality factor enhancement techniques for inductor and transformer

ABSTRACT Quality factor enhancement for inductor and transformer has been achieved by the techniques such as fabricating the inductor and transformer on a glass substrate having high resistivity and by fabricating the inductor far away the silicon substrate and within this distance use of air, high-resistive silicon and silicon nitride as cavity. The simulation results are obtained by using the tool ASITIC (analysis and simulation of inductor and transformer for integrated circuits). Inductor is a key component in radio frequency (RF)-based devices and shows poor RF characteristics when it is formed on a Si substrate chip. It happens because of substrate-based RF losses and parasitics arised due to inter spiral tracks. Fabrication of inductor and transformer on a glass substrate results in a high quality factor as well as high self-resonance frequency which shows good prospects in various radio frequency integrated circuits applications.