Sunyeol Jeon

Characteristics of the ZnO thin film transistor by atomic layer deposition at various temperatures

ZnO thin films were deposited by atomic layer deposition (ALD) at various temperatures and the resulting electrical and chemical properties were examined. The fraction of O–H bonds in ZnO films decreased from 0.39 to 0.24 with increasing processing temperatures. The O/Zn ratio decreased from 0.90 at 70 °C to 0.78 at 130 °C. The carrier concentration and resistivity changed sharply with decreasing temperature. The ZnO thin film transistors (TFTs) were fabricated at processing temperatures of 70 to 130 °C and the electrical properties of the TFT were as follows: the field-effect mobility ranged from 8.82 × 10−3 to 6.11 × 10−3 cm2 V−1 s−1, the on/off current ratio ranged from 1.28 × 106 to 2.43 × 106, the threshold voltage ranged from −12.5 to 14.7 V and the subthreshold swing ranged from 1.21 to 24.1 V/decade. The electrical characteristics of the ZnO TFT were enhanced as the processing temperature decreased.

Structural and Electrical Properties of ZnO Thin Films Deposited by Atomic Layer Deposition at Low Temperatures

In this study, ZnO thin films were deposited by atomic layer deposition (ALD) at various process temperatures. The purpose of this paper was to investigate the controllability of the preferred orientations of ZnO thin films by varying the process temperature and to determine the effect of the preferred orientations on the electrical properties of the films. The process temperature was varied from 70 to 250°C at several increments while the other ALD process parameters were fixed. The deposition rates and uniformities, crystal structures, and electrical properties of these films were evaluated at the various process temperatures. At process temperatures of 70 and 90°C, ZnO thin films showed strong (002) preferred orientations with cylindrical, fine, columnar crystal structures, almost a 1:1 stoichiometric chemical ratio of Zn to O, and n-type carrier concentrations in the range of 10 16 cm -3 with resistivities of 0.1-1 Ω cm. ZnO thin films deposited at temperatures higher than 110°C had wedge-shaped crystal structures, high oxygen deficiencies, and higher n-type carrier concentrations up to 10 20 cm -3 than the films deposited at lower temperatures.

Al2O3 buffer in a ZnO thin film transistor with poly-4-vinylphenol dielectric

We compared the characteristics of bottom-gate ZnO-thin film transistors using poly-4-vinylphenol (PVP) and PVP/Al2O3 dielectrics. The PVP dielectric is more hydrophobic than the PVP/Al2O3 dielectric and is not useful for TFT devices because of its high leakage current density, but this leakage current density can be significantly reduced by inserting Al2O3. We deposited ZnO and Al2O3 films by atomic layer deposition (ALD) because it is a low-temperature process. The ZnO-TFTs with either a PVP or a PVP/Al2O3 dielectric exhibit typical field-effect transistor characteristics with n-channel properties. The ZnO-TFT containing PVP/Al2O3 exhibits clear pinch-off and excellent saturation with an enhanced mode operation. The on/off ratio of 7.9 × 104 for the device containing the hybrid dielectric is about three orders of magnitude higher than the ratio of 47 for the device containing PVP. The subthreshold gate swings are 12 V/decade for the TFT containing PVP and 1.2 V/decade for the TFT containing PVP/Al2O3. The density of the interface trap state is significantly lower in the device containing PVP/Al2O3 than in the ZnO-TFT containing PVP. The saturation mobility was 0.05 and 0.8 cm2 V−1 s−1, respectively, in the TFTs containing PVP and PVP/Al2O3.

Physical and Electrical Properties of Hafnium–Zirconium–Oxide Films Grown by Atomic Layer Deposition

We deposited HfO 2 , ZrO 2 , and Zr x Hf 1-x O 2 films having different ZrO 2 contents on Si substrates by atomic layer deposition at 300°C and investigated their physical and electrical characteristics. The HfO 2 and ZrO 2 films with thicknesses of about 20 nm exhibited crystalline structures composed of monoclinic and tetragonal phases, respectively. As the ZrO 2 content in the hafnium-zirconium-oxide was increased, the ratio of the tetragonal phase seen in the crystal increased. These changes in crystal phase led to changes in electrical properties. The crystalline phases and electrical properties of the hafnium-zirconium-oxide films exhibited a strong dependence on their Hf/Zr composition ratio.

Characteristics of Hafnium–Zirconium–Oxide Film Treated by Remote Plasma Nitridation

Characteristics of hafnium-zirconium-oxide films, with and without remote plasma nitridation, have been investigated. The films were created by atomic layer deposition. After deposition, remote plasma nitridation was performed. Nitrogen atoms were successfully incorporated into the hafnium-zirconium-oxide films. As-deposited hafnium-zirconium-oxide film showed a partially crystallized structure. Remote plasma treatment of the hafnium-zirconium-oxide film can effectively suppress the crystallization of the film during rapid thermal annealing. The annealed hafnium-zirconium-oxide film treated by remote plasma nitridation showed a lower equivalent oxide thickness (EOT) and a lower leakage current density than a non-nitrided sample with the same physical thickness. The EOTs of the mixed oxide films with and without nitridation were approximately 1.8 and 2.0 nm, respectively, and the leakage current densities of the films were 5.5 X 10 -8 and 9.2 X 10 -6 A/cm 2 , respectively.

Study of Nickel Silicide Thermal Stability Using Silicon-on-Insulator Substrate for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transisor Device

The thermal stability of nickel silicide (NiSi) on a silicon-on-insulator (SOI) substrate after postsilicidation annealing (550–700 °C) is discussed in this paper. Nickel silicide technology, used for nanoscale complementary metal oxide semiconductor (CMOS) field-effect transistor (FET) devices, has a fundamental problem of thermal stability. Three different Pd concentrations in Ni–Pd alloy, 1, 5, and 10 at. %, were used to study the thermal stability of nickel silicide formed by a silicidation process. The Ni–Pd (10%) sample showed good thermal stability upon annealing at temperatures up to 700 °C for 30 min. Only a low-resistivity mononickel silicide (NiSi) phase peak was observed by X-ray diffraction (XRD) measurement, which was confirmed by Auger electron spectroscopy (AES) analysis. Uniformly formed nickel silicide with a good interface profile was obtained using the Ni–Pd (10%) sample according to field-emission scanning electron microscopy (FE-SEM) measurement. However, the Ni–Pd (5%) sample produced high-resistivity nickel disilicide (NiSi2) after annealing at 650 °C for 30 min. Four different layer structures, Ni, Ni/TiN, Ni/Co/TiN, and Ni–Pd (10%)/Co/TiN, were also used for further study. Among these structures, the Ni–Pd (10%)/Co/TiN layer structure had good thermal stability upon annealing at temperatures up to 700 °C, while the other structures deteriorated due to agglomeration above 550 °C.

Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device

The effects of a strained silicon layer on the thermal stability of nickel (germano)silicide for nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET) devices are discussed in this study. Three different thicknesses, 5, 13, and 40 nm, of silicon layers on silicon germanium (SiGe) were prepared for this experiment. The effects of the silicidation rapid thermal annealing (RTA) temperature and postsilicidation annealing temperature for the different silicon layer thicknesses were studied. For comparison, a bulk silicon substrate and a SiGe substrate were also used. Silicides with the thin strained silicon layers (5 and 13 nm) on SiGe showed good thermal stability in this study. However, the other silicides using bulk silicon, 40-nm-thick silicon on SiGe, and the SiGe substrate underwent degradation due to silicide agglomeration during annealing. A SiO2 layer was found on the silicide using the SiGe substrate. In this study, several analysis methods such as four-point probe measurement, field-emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), and Auger electron spectroscopy (AES) were used for detailed study.

GPS antenna using a system ground as a radiator

This paper presents global positioning system (GPS) antenna embedded in printed circuit board (PCB). The proposed antenna uses two chip capacitors and one chip inductor in order to control resonance frequency and degree of coupling, respectively. The effects of these lumped components are analyzed by using an equivalent circuit model of the proposed antenna. Bandwidth under voltage standing wave ratio (VSWR) of 3:1 is 45 MHz from 1540 MHz to 1585 MHz and it sufficiently covers GPS operation band.