Susana Paton

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction

This work presents a system level model of the clock jitter influence in certain types of continuous time sigma delta modulators. The model helps the design of such modulators by speeding up the simulations, predicting analytically the SNR degradation and providing a practical way to minimize the jitter sensitivity of the modulator. Simulations and theoretical developments are contrasted with measurements in a real chip.

A 0.1 mm

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm2.

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This paper presents a new superregenerative receiver architecture. This receiver uses an oscillator based on a transmission line. By periodically changing the oscillator pole locations, the receiver is able to translate the carrier phase information into a low-pass signal. This circuit may also be used as a band-pass sampler for low-level RF signals.

, Wide Bandwidth Continuous-Time

This work presents an area- and power-efficient realization of a new time-encoding oversampling converter (TEOC) consisting of a third-order continuous time (CT) loop filter and a self-oscillating pulse-width modulator (PWM). The modulator displays similar performance to that of a standard multibit CT-ΣΔ modulator but has the complexity of a single bit design. The time-encoding quantizer (TEQ) is implemented inside a ΣΔ modulator by replacing a multibit quantizer. An innovative TEQ is used to overcome design issues in a 1.0 V supply-voltage 65 nm digital CMOS technology. The TEQ allows an exchange of amplitude-resolution by time-resolution. The approach of time-resolution alleviates the scaling difficulties of mixed-signal circuits in nano-scale technologies. The TEOC features a 63 dB dynamic-range and a peak-SNDR of 61 dB over a 20 MHz signal bandwidth. Clocked at 2.5 GHz, the complete ADC consumes 7 mW from a single 1.0 V supply, including also the reference buffers. The ADC core results in an attractively small area of 0.08 mm2 and in a figure-of-merit (FoM=Pwr/2 · BW · 2ENOB) of 0.17 pJ/conversion-step.

\Sigma\Delta

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

ADC Based on a Time Encoding Quantizer in 0.13

This paper addresses the design of continuous time sigma delta modulators based on delay elements. The proposed modulators use resonators implemented with transmission lines instead of capacitive integrators. The advantage of such modulators is the desensitization of the modulator behavior against time varying effects in the feedback path such as clock jitter and DAC pulse distortion. Another advantage is the possibility of including excess loop delay as a component of the NTF of the modulator.

\mu

A novel discrete time cascaded sigma-delta modulator topology is presented. The overall noise transfer function (NTF) may be modified by means of an additional error feedback in the analog circuitry. Mismatch properties do not depend on the additional feedback path, and therefore the signal to noise ratio (SNR) may be improved by proper location of NTF zeros. Moreover, one of the NTF zeros may be programmable by means of analog trimming while digital cancellation filters remains unaffected. A low oversampling ratio (OSR) 2-2 cascade sigma-delta modulator is presented as a design example.

m CMOS

This paper evaluates two techniques to improve the linearity of the main feedback D/A converter in multi-bit continuous-time sigma-delta modulators (CT-SDM). A self-calibrated current-steering (SCCS) implementation of the D/A converter is compared to the usage of a data-weighted averaging (DWA) algorithm on the selection of uncalibrated D/A-elements. Two test-chips including the two different solutions are presented and measurement results are compared. Clocked at 300 MHz, the two CT-SDMs achieve a dynamic range of 67 dB (DWA) and 70 dB (SCCS), respectively, over an analog bandwidth of 15 MHz.

A superregenerative receiver for phase and frequency modulated carriers

This paper presents the system level design of a novel multi-bit Sigma-Delta (ΣΔ) ADC architecture that replaces the flash quantizer and mismatch corrected multi-bit DAC of a ΣΔ modulator by an integrating quantizer and a Pulse-Width Modulated DAC. This converter achieves the resolution of a multi-bit design using single-bit circuitry. The quantizer of this modulator is similar to a classical Dual-Slope integrating converter, but the charge residue in the integrator at the end of each conversion cycle is stored for the next conversion, providing first order noise shaping. As an example, the system level performance of a second-order multi-bit ¿¿ ADC using this new architecture has been evaluated. Also, circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC could achieve an ENOB = 13 bits in a signal bandwidth of 2 MHz using conventional CMOS technology, which could be suitable for wireless communication standards.