Sushanta K. Mandal

Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing

Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process technology using Cadence EDA tool.

A 6–17 GHz linear wide tuning range and low power ring oscillator in 45nm CMOS process for electronic warfare

A two-stage CMOS Voltage Controlled Ring Oscillator (VCRO) with very low power consumption has been designed in 45 nm CMOS process which operates at 1-V supply voltage. The circuit is simulated in GPDK 45 nm technology in Cadence environment. The simulation result shows wide tuning range from 6 GHz to 17 GHz and the oscillator can be used for electronic warfare application. It has also very low power consumption of about 3 μW. The phase noise of this ring oscillator is found to be -78 dBc/Hz @ 10 MHz offset which can be improved by using more number of stages.

A Novel Modeling Technique for Operational Amplifier Using RBF - ELM

This paper formulates a new modeling technique for the analog circuits like OPAMP (Operational Amplifier). One of the fastest learning techniques, extreme learning machine along with best suitable kernel Radial Basis Function has been implemented for modeling. The simulated result shows that the training speed is very high and can handle a large set of data without compromising accuracy.

Low-Power, High-Speed, Indirect Frequency-Compensated OPAMP with Class AB Output Stage in 180-nm CMOS Process Technology

In this paper, the design of low-power, high-speed, two-stage, indirect frequency-compensated operational amplifier is presented. The OPAMP employs split-length devices and class AB output stage. Split-length technique is employed both in load device as well as in differential-pair device. The split-length device enhances the phase margin (PM) and unity gain bandwidth (UGB) while maintaining lower supply voltage. The class AB output stage provides a faster settling time and reduced power dissipation. Simulations of the proposed circuits were carried out in cadence specter on 180-nm process technology at a supply voltage of 1.6 V. The proposed split-length current mirror load OPAMP exhibits power dissipation of 82 µW, UGB of 43.26 MHz, and PM of 79.25°. Similarly, the proposed split-length differential-pair OPAMP exhibits a power dissipation of 78 µW, UGB of 49.71 MHz, and PM of 85.34°.

A low offset fast settling rail-to-rail stable operational amplifier in 180 nm technology

This work presents the design of a modified two stage operational amplifier in 0.18 μm CMOS technology. The main objective of the design is to make a trade-off between offset voltage and power consumption while maintaining rail-to-rail output swing and high phase margin. For this purpose, transistors with controlled region of operation are included to the output stage. Simulation is done in Cadence Spectre with 1.8V power supply. Simulation results show that the designed OPAMP consumes 616.31 μW power with high phase margin of 70.6° and very low offset voltage of 16.91 μV, maintaining rail-to-rail output swing.