Swapnadip Ghosh

Origin and removal of stacking faults in Ge islands nucleated on Si within nanoscale openings in SiO2

We have previously reported that Ge films formed after nucleation of Ge islands within nanometer size openings in SiO2 and their subsequent coalescence over the SiO2 template exhibit threading dislocation densities below 106 cm−2. However, these films contain a density of twin/stacking fault defects on the order of 5 × 1010 cm−2 that emanate primarily from the Ge-SiO2 interface. Most of these faults self-terminate within 200 nm of the interface; however, a total of 5 × 107 cm−2 propagate to the Ge surface. These defects are found to be detrimental to the morphology and minority carrier lifetime in III-V films integrated onto the Ge-on-Si virtual substrates. We have found that annealing the Ge islands during the initial stage of coalescence eliminates stacking faults, but further Ge growth leads to a film containing a threading dislocation density of 5 × 107 cm−2. To explain the origin of the twin/stacking fault defects in the Ge films and their removal after annealing Ge islands, we have studied the Ge is...

Effect of threading dislocation density and dielectric layer on temperature-dependent electrical characteristics of high-hole-mobility metal semiconductor field effect transistors fabricated from wafer-scale epitaxially grown p-type germanium on silicon substrates

We report the electrical characteristics of Schottky contacts and high-hole-mobility, enhancement-mode, p-channel metal semiconductor field effect transistors (MESFETs) fabricated on Ge epitaxially grown on Si substrates. The Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. The device performance is characterized primarily as a function of threading dislocation density in the epitaxial Ge film (2 × 107, 5 × 107, 7 × 107, and 2 × 108 cm−2) and dielectric layers (SiO2, Al2O3, and HfO2) inserted between gate metal and Ge. The thin dielectric layers (∼1.3 nm) are used to unpin the Fermi level. The device performance improves with decreasing threading dislocation density and the use of HfO2. The hole mobility in the Ge film with 2 × 107 cm−2 dislocation density, obtained from Hall measurements, is 1020 cm2/V-s. Capacitance-voltage measurements on Schottky contacts provide the energy-dependent interfacial trap density of 6 × 1011 cm−2 eV−1, while current...

Experimental and theoretical investigation of thermal stress relief during epitaxial growth of Ge on Si using air-gapped SiO2 nanotemplates

We demonstrate that SiO2 nanotemplates embedded in epitaxial Ge grown on Si relieve the stress caused by the thermal expansion mismatch between Ge and Si. The templates also filter threading dislocations propagating from the underlying Ge-Si interface, reducing the density from 9.8 × 108 to 1.6 × 107 cm−2. However, we observe that twin defects form upon Ge coalescence over the template, and the density is approximately 2.8 × 107 cm−2. The coalescence occurs without direct contact with SiO2, leaving a void between Ge and SiO2 that further reduces the thermal stress. The stress obtained from finite element modeling corroborates the experimental observation.

Stress-directed compositional patterning of SiGe substrates for lateral quantum barrier manipulation

While vertical stacking of quantum well and dot structures is well established in heteroepitaxial semiconductor materials, manipulation of quantum barriers in the lateral directions poses a significant engineering challenge. Here, we demonstrate lateral quantum barrier manipulation in a crystalline SiGe alloy using structured mechanical fields to drive compositional redistribution. To apply stress, we make use of a nano-indenter array that is pressed against a Si0.8Ge0.2 wafer in a custom-made mechanical press. The entire assembly is then annealed at high temperatures, during which the larger Ge atoms are selectively driven away from areas of compressive stress. Compositional analysis of the SiGe substrates reveals that this approach leads to a transfer of the indenter array pattern to the near-surface elemental composition, resulting in near 100% Si regions underneath each indenter that are separated from each other by the surrounding Si0.8Ge0.2 bulk. The “stress transfer” process is studied in detail us...

Symmetry-breaking nanostructures on crystalline silicon for enhanced light trapping in thin film solar cells.

We introduce a new approach to systematically break the symmetry in periodic nanostructures on a crystalline silicon surface. Our focus is inverted nanopyramid arrays with a prescribed symmetry. The arrangement and symmetry of nanopyramids are determined by etch mask design and its rotation with respect to the [110] orientation of the Si(001) substrate. This approach eliminates the need for using expensive off-cut silicon wafers. We also make use of low-cost, manufacturable, wet etching steps to fabricate the nanopyramids. Our experiment and computational modeling demonstrate that the symmetry breaking can increase the photovoltaic efficiency in thin-film silicon solar cells. For a 10-micron-thick active layer, the efficiency improves from 27.0 to 27.9% by enhanced light trapping over the broad sunlight spectrum. Our computation further reveals that this improvement would increase from 28.1 to 30.0% in the case of a 20-micron-thick active layer, when the unetched area between nanopyramids is minimized with over-etching. In addition to the immediate benefit to solar photovoltaics, our method of symmetry breaking provides a useful experimental platform to broadly study the effect of symmetry breaking on spectrally tuned light absorption and emission.

Modeling and simulation of compositional engineering in SiGe films using patterned stress fields

Semiconductor alloys such as silicon–germanium (SiGe) offer attractive environments for engineering quantum-confined structures that are the basis for a host of current and future optoelectronic devices. Although vertical stacking of such structures is routinely achieved via heteroepitaxy, lateral manipulation has proven much more challenging. We have recently demonstrated that a patterned elastic stress field applied, with an array of nanoscale indenters, to an initially compositionally uniform SiGe substrate will drive atomic interdiffusion leading to compositional patterns in the near-surface region of the substrate. While this approach may offer a potentially efficient and robust pathway to producing laterally ordered arrays of quantum-confined structures, optimizing it with respect to the various process parameters, such as indenter array geometry, annealing history, and SiGe substrate thickness and composition, is highly challenging. Here, a mesoscopic model based on coarse-grained lattice kinetic Monte Carlo simulation is presented that describes quantitatively the atomic interdiffusion processes in SiGe alloy films subjected to applied stress. We first show that the model provides predictions that are quantitatively consistent with experimental measurements. Then, the model is used to investigate the impact of several process parameters such as indenter shape and pitch. We find that certain indenter configurations produce compositional patterns that are favorable for engineering lateral arrays of quantum-confined structures.

High-Mobility MOSFETs Fabricated on Continuous, Wafer-Scale Ge Films Epitaxially Grown on Si

We report the material characterization of continuous, wafer-scale Ge films epitaxially grown on Si by molecular beam epitaxy. The material quality of Ge is further tested by fabricating high-mobility, long-channel MOSFETs. Our growth technique makes use of a thin chemical SiO₂ template with nanoscale windows and carefully timed thermal annealing during the initial stage of island coalescence. The resulting defect density in n- and p-type Ge is ~2 × 10⁵ and 5 × 10⁷ cm^-2. The MOSFETs are then fabricated on these substrates, where the gate-stack consists of Ti/HfO₂/GeO_xN_y/Ge-on-Si. The GeO_xN_y interlayer is used to effectively passivate the Ge surface. The subthreshold slope is ~100 and ~200 mV/decade for p- and n-MOSFETs, compared with ~80 mV/decade for p-MOSFETs built on bulk-Ge substrates. The p- and n-MOSFETs also show enhanced peak effective hole and electron mobilities of 400 and 950 cm²/V-s that are 82% and 30% increase over the universal mobilities in Si.

Light trapping enhancement in thin film solar cells by breaking symmetry in nanostructures

We experimentally demonstrate highly efficient light-trapping structures that is achieved by breaking the symmetry in inverted nanopyramids on c-Si. The fabrication of these structures is cost-effective and scalable. Our optical measurement for the structures on 10-μm-thick c-Si cells shows the Shockley-Queisser efficiency of 27.9%. We further fabricate plasmonic metal structures on the symmetry-breaking inverted nanopyramids. When a light-absorbing polymer layer is deposited on top of the plasmonic structures, we observe that the plasmonic light trapping exceeds the Lambertian limit. The remarkable light trapping increases the short circuit current by 2.5 times. We expect the symmetry-breaking structures to be broadly applicable to thin-film solar cells.

Symmetry-breaking nanostructures for enhanced light-trapping in thin film solar cells

We introduce a manufacturable method to break the symmetry in inverted nanopyramids on c-Si. This method broadly enhances light trapping and would increase the efficiency from 25 to 26.4% for thick c-Si cells. We further use the nanopyramids as a template to deposit plasmonic metal structures and demonstrate enhanced light absorption in organic solar cells. The enhancement exceeds 100% in some cases by concentrating the plasmonic bands tuned to the polymer absorption. The result agrees well with our measured surface plasmon polariton band structures. We expect our approach to be broadly applicable to thin-film solar cells.