Sylvain Engels

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1].

A predictive bottom-up hierarchical approach to digital system reliability

This work has introduced a new electrical aging assessment framework for digital systems, based upon strong physics-based foundations and an adequate bottom-up approach which enables propagating accurate reliability knowledge at system level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

Logical effort model extension to propagation delay representation

The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combinatorial paths for satisfying tight timing constraints. This is due to the inability of the logical effort model in capturing I/O coupling and input ramp effects that distinguish the transition time from the propagation delay. Using an analytical modeling of the supply current that flows in simple gates during their switching process, this paper introduces an extension of the logical effort model that considers the I/O coupling capacitance and the input ramp effect. Validation of this model is performed on 130-nm STMicroelectronics technology. A compact representation of CMOS library timing performance is given as a possible application of the proposed model. The choice of sampling points to be used in look-up tables as representative steps of the design range is also discussed

A Fine-Grain Variation-Aware Dynamic

In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independent voltage-frequency island. This architecture has been implemented on a 32 nm globally asynchronous locally-synchronous MPSoC. It shows up to 18.2% energy gains thanks to local adaptability compared with a global dynamic voltage and frequency scaling approach using 25% timing margins between slow and nominal process, by reducing margins to 60 ps of the real process. These gains are obtained for a total area overhead of 10% including local frequency/voltage actuators, sensors, and digital controller.

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The increase of within-die variations and design margins is creating a need for statistical design methods. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts occurring during production. This method is first validated for 90nm and 65nm processes. Finally, this statistical timing analysis is applied on basic ring oscillators to evaluate the timing margins introduced at the design level by the traditional corner based approach.

-Hopping AVFS Architecture on a 32 nm GALS MPSoC

A Low-Density Parity-Check (LDPC) codec circuit is implemented in a 65nm Low-Power Partially-Depleted SOI (LP PD-SOI) technology, as well as in a “conventional” Low-Power Bulk technology for a fair comparison. PD-SOI allows to increase maximum frequency versus bulk at a given voltage, and to decrease dynamic power versus bulk at a given frequency. Thanks to a digital power-switching technique specifically optimized for LP PD-SOI, we demonstrate a leakage current reduction versus bulk 65nm LP implementation, solving one of the most critical problems of PD-SOI technology, as identified in previous publications.

A simple statistical timing analysis flow and its application to timing margin evaluation

With the scaling of technology, the variability of timing performances of digital circuits is increasing. In this paper, we propose a first order analytical modeling of the standard deviations of basic CMOS cell timings. The proposed model is then used to define a statistical characterization protocol which is fully compliant with standard characterization flows. Validation of this protocol is given for a 90nm process.

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

Statistical characterization of library timing performance

This paper aims at introducing a safe voltage scaling and body biasing methodology for Low-Density Parity Check (LDPC) hard-wired IP. The proposed methodology allows an efficient post-silicon tuning of the LDPC, and the performances can be adapted to High Speed mode, or Low Operating Power mode, or Low Standby Power mode requirements. Concrete 45nm silicon results are introduced in this paper to demonstrate the added value of the methodology. More precisely, it is shown that running the High Performance mode leads to +24% on circuit maximum operating frequency. And the Low Standby Power mode results on x0.73 leakage minimization. The proposed adaptive LDPC encoder/decoder can remove some barriers to the adoption of long LDPC codes on portable devices.

Bottom-up digital system-level reliability modeling

The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through a non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in sub-micrometer domain due to its inability in capturing input slope and shielding effects.This paper presents an analytical expression for the transition time and the switching delay of an RC interconnect, including the line input and output drivers. Based on a previously developed model of the inverter transition time and the switching delay, we propose a model of the shielding capacitance effect on the input driver. We then determine the transition time of the output driver and the switching delay of the complete structure for different size of input drivers. We validate these analytical expressions with respect to electrical simulations, on 130 and 90 nm processes, using the eldos transmission line model.