Sylvain Feruglio

FPGA implementation of reconfigurable ADPLL network for distributed clock generation

This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.

High level modeling of signal integrity in field bus communication with SystemC-AMS

This paper presents a novel method for modeling the functionality of a mixed-signal system, and analyzing its signal integrity (SI) at a high-level of abstraction with SystemC-AMS. Our model includes on a unique platform a functional module and a non-functional module. The functional module represents the operative behavior of the system and the non-functional module, based on neural network techniques, displays the SI characteristics of the system. The proposed method is demonstrated by modeling field bus communication system with two nodes. We achieved an error of about 3% for the neural network based Time Data Flow (TDF) model with respect to a RLC Electrical Linear Networks (ELN) model.

A CMOS Buried Quad p-n Junction Photodetector Model

A buried quad junction (BQJ) photodetector has been designed and fabricated with a high-voltage CMOS process. It implements four vertically stacked p-n junctions with four different spectral responses. This feature allows high spectral discriminating ability, greater than both conventional buried double junction and buried triple junction detectors. In this paper, we propose a SPICE-like model, based on the physical properties of the device structure. The proposed model has been integrated in EDA software. It could be used for rapid and reliable design of system on chip, integrating the BQJ sensor, and its signal processing. The analytical expressions of the four BQJ photocurrents, as well as dark currents, have been developed. The spectral characteristics of the photodetector, computed with the proposed model, have been compared with those from TCAD simulations and experimental measurements. The analytical is close to the measurement with an average error on spectral responses in the range of 3%-17%, depending on the considered junction.

CMOS buried multi-junction (BMJ) detector for bio-chemical analysis

The CMOS buried multi-junction (BMJ) detector with multiple outputs has distinct spectral responses that may be exploited for applications such as bio-chemical analysis. We tackle here dark current issue by identifying different components inside the detector structure. The identification methods are based on the observation of bias and temperature dependence, as well as measurements of test detector chip integrating different design variations. Surface thermal generation may become predominant when the detector size shrinks, thus causing dark current degradation. To prevent this effect, we propose a low-sized detector structure with passivation of all its surrounding Si/SiO2 interface areas. Also for the detector readout, we present a multi-channel charge-amplifier architecture with noise analysis. Effects of noise coming from amplifiers and related to the coupled detector’s dynamic conductances are illuminated. To pick up weak signals, synchronous detection can be implemented. A BDJ (Buried Double Junction) detector chip designed with a switched-phase architectural approach gives a minimum detectable signal of 15μlx@555nm or 1μlx@555nm at 27°C or – 10°C, for an integration time of 3s or 45s respectively.

Investigation of electrical characteristics of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. We have investigated its characteristics using I-V measurements, C-V split method and both two- and three-level charge pumping techniques. Its tunable-threshold and multi-threshold features were verified. Its surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process.

Opto-Electrical Modeling of CMOS Buried Quad Junction Photodetector

A Buried Quad Junction (BQJ) PhotoDetector (PD), composed of four vertically-stacked p-n junctions, has recently been implemented and fabricated in CMOS technology. The detector, providing four different spectral responses, has higher spectral discriminating ability than both conventional Buried Double Junction (BDJ) and Buried Triple Junction (BTJ) detectors. For rapid system design integrating of the BQJ PD, we propose a BQJ SPICE-like model based on the physical properties of the device structure. The analytical expressions of the four BQJ photocurrents have been developed. Dark currents as well as intrinsic noise can also be evaluated by computations. Results have been compared with both TCAD simulations and measurements. Our model shows a good agreement with measurements and the mean relative error on spectral response prediction is between 6 % and 17 % in function of the observed junction.

A self-sufficient digitally controlled ring oscillator compensated for supply voltage variation

A self-sufficient Giga-Hertz digitally controlled ring oscillator for clock distribution network is presented in this paper. It features a high supply insensitivity in order to mitigate the additional jitter due to supply noise. This is achieved by inducing a mutual compensation between the oscillation frequency parameters that are affected by the supply voltage variations. The proposed method can be easily implemented and takes advantage of the deep sub-micrometer effects peculiar to topical CMOS technologies. We demonstrate by simulations that this approach remains efficient over process variations despite the reliability issue of short channel MOS transistors.

High-Level Virtual Prototyping of Signal Integrity in Bus Communication

In this paper, a novel methodology for high-level modeling of bus communication in embedded systems is introduced. It allows the dynamic evaluation of their signal integrity (SI) characteristics at the virtual prototyping step (i.e., before physical realization). The method is based on the association of functional and nonfunctional modules. Functional modules represent the ideal behavior of the system, while nonfunctional modules use neural networks to model SI effects. This approach was implemented in SystemC-AMS, using the timed data flow model of computation. The method is illustrated by a Universal Serial Bus (USB) 3.0 application, where modular and parameterizable models are introduced. The method achieved good accuracy (<;5%) while allowing significant simulation speedup (up to 2000 times), compared with SPICE-based reference models. This methodology can be used to perform an early SI analysis in the virtual prototyping of bus communication in the embedded systems.

In vivo NIRS monitoring in pig Spinal Cord tissues

Little is known about the processes occurring after Spinal Cord damage. Whether permanent or recoverable, those processes have not been precisely characterized because their mechanism is complex and information on the functioning of this organ are partial. This study demonstrates the feasibility of Spinal Cord activity monitoring using Near Infra-Red Spectroscopy in a pig animal model. This animal has been chosen because of its comparable size and its similarities with humans. In the first step, optical characterization of the Spinal Cord tissues was performed in different conditions using a spectrophotometer. Optical Density was evaluated between 3.5 and 6.5 in the [500; 950] nm range. Secondly, adapted light sources with custom probes were used to observe autonomic functions in the spine. Results on the measured haemodynamics at rest and under stimulation show in real time the impact of a global stimulus on a local section of the Spinal Cord. The photoplethysmogram signal of the Spinal Cord showed low AC-to-DC ratio (below to 1 %).

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (VTH=0.59V, S=90mV/dec) and simulations (VTH=0.50V, S=92mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO2 interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current-voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.