Syotaro Ono

Multi Chip Module with Minimum Parasitic Inductance for New Generation Voltage Regulator

This paper analyzes the effects of parasitic inductances over the conversion efficiency of DC-DC converters by using Spice simulator. It was found that the self-turn-on of the low side MOSFET is triggered by large body diode reverse recovery current. A new multi chip module (MCM) has been developed in order to suppress the self-turn-on of the LS MOSFETs and to reduce the parasitic inductances. The MCM also has unique upper surface cooling feature. The MCMs successfully improve the conversion efficiency by using the MOSFETs with reduced body diode reverse recovery. Conversion efficiency can be further improved by reducing the gate resistance and optimizing the dead time

30V new fine trench MOSFET with ultra low on-resistance

The present paper proposes a new ultra low on-resistance trench MOSFET. The proposed device is characterized by the narrow high resistance n-epi layer between the two trench gates and the thin n-drift layer, which lies between the trench bottom and the n+ substrate. The high resistance n-epi between the trenches is always depleted because of the built-in potential of the p+ gate poly, resulting in the normally-off characteristics without p-base. The thin n-drift layer enables the use of thin gate oxide. The optimum doping concentration and thickness of the n-drift is chosen so that the on-resistance is minimized. The proposed trench MOSFET experimentally achieved a 33(V) drain-source blocking voltage and a 10m/spl Omega/mm/sup 2/ specific on-resistance at V/sup GS/=10V. This is the lowest Ron value ever reported.

High density MOSBD (UMOS with built-in Trench Schottky Barrier Diode) for Synchronous Buck Converters

We proposed a new MOSBD, which integrates MOSFET and Schottky barrier diode (SBD) in a single chip. The features of the device are that the SBD are fabricated on fine mesa of less than 0.2mum, surrounded by trenches and optimally distributed inside the high density UMOS. We show that the distributed layout of the SBD inside the MOSFET cells is effective to reduce the reverse recovery charge (Qrr), output charge (QOSS(SBD)) and the forward voltage drop (VfSBD ). In addition, integrated high density UMOS realizes low on-resistance of 18mOmegamm2 at Vgs=4.5V. The developed MOSBD achieved 46% reduction of chip size, compared to conventional MOSBD and low leakage current even in 175deg C high temperature condition. The developed MOSBD successfully increases the conversion efficiency, compared to the discrete solution of MOSFET with external SBD

Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class Semi-Super Junction MOSFET

We report the experimental results detailed about the n-buffer layer (n-BAL: n-bottom assist layer) of 600 V-class semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (R_onA) and the breakdown voltage (V_B), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio T_BAL-ratio and the doping concentration N_BAL were varied in this work. As a result, the VB=750 V, the R_onA=24.6 mOmegacm², the maximum avalanche current density J_AP=292 A/cm² (I_AP=7.6A, E_AS=1.25 J/cm²), and softness factor=0.277 were obtained with the structure of T_BAL-ratio=27% and N_BAL=1.0x10¹⁵cm^-3. The demonstration results showed that NPT (non punch through)-type design (with high T_BAL-ratio and high N_BAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (punch through)-type design.

Influence of carrier lifetime control process in superjunction MOSFET characteristics

This paper reports device characteristics of superjunction (SJ) MOSFETs employed with platinum (Pt) doping or electron irradiation processes for high speed recovery operation of the internal body diode. For the inverter application, high speed recovery operation of the internal body diode is necessary. 600 V-class SJ-MOSFETs were fabricated with a lifetime control process. In this paper, the influence of the carrier lifetime control process upon the on-resistance, leakage current and withstanding capability are reported. The lifetime control process modulates the static characteristics, and it is difficult to obtain the high speed operation with trr <; 100 ns maintaining both low on-resistance and low leakage current. However, the withstanding capability is not problematic due to suppressing the carrier concentration by the short lifetime.

Development of 600V-class trench filling SJ-MOSFET with SSRM analysis technology

600V-class superjunction (SJ)-MOSFETs were developed using our original high-resolution Scanning Spread Resistance Microscopy (SSRM) analysis technology [1] for optimization of trench filling process for the first time. The SSRM analysis is a powerful tool for the SJ structure design, because it can be achieved the measurement of two- dimensional (2D)-carrier profile and detect of minute voids. The measured profile was applicable for device simulation of the SJ-Diode and the estimated breakdown voltage was in good agreement with the experimental values. By the feed back of these results to the trench filling process, the breakdown voltage was increased and the trade-off characteristics between the breakdown voltage and the specific on-resistance were achieved to 685V/16.5mΩcm2 in the fabricated SJ-MOSFET.

Suppression of switching loss dependence on charge imbalance of superjunction MOSFET

We discuss switching behavior of superjunction (SJ)-MOSFETs in terms of interaction between MOS gate structure and charge imbalance (CIB) of SJ structure. Resistive load switching behavior of SJ-MOSFET was analyzed by device simulation. CIB changes the gate voltage transient behavior between gate threshold voltage and gate plateau voltage via modification of the potential near the gate. We found key parameter which determines the effect of MOS structure and layout upon loss, and indicated robust MOS gate design and layout from the perspective of switching loss. Finally, we confirmed the conclusion by experiment.

Temperature dependence of single-event burnout for super junction MOSFET

Single-Event Burnout (SEB) is one of the catastrophic failure effects that could cause destruction of a MOSFET. In the present work, we experimentally obtained the dependence of SEB tolerance of Super-junction (SJ) MOSFET on temperature and studied the mechanism of the dependence of SEB failure rate on temperature by simulation.

The optimal profile design for SJ-MOSFET fabricated by double-ion-implantation and multi-epitaxial method

We investigated the profile dependency of specific on-resistance (RonA) under high- temperature and high-current-density conditions for 600 V-class semi-superjunction MOSFETs fabricated by the double-ion-implantation and multi-epitaxial method, for the first time. The column doping profile is an important design parameter for the RonA characteristics because the profile affects the electron mobility (mue) in the drift region. The n-column profile was modulated by the column diffusion time (tdiff) in this experiment. The optimal tdiff achieved minimal RonA under the high-temperature and high-current-density conditions.