T.H. Low

Creep and fatigue characterization of lead free 95.5Sn-3.8Ag-0.7Cu solder

The creep and fatigue properties of 95.5Sn-3.8Ag-0.7Cu lead free solders were investigated. Steady-state creep behavior for 95.5Sn-3.8Ag-0.7Cu bulk solder specimens were compared to reported creep test data for solder joints. Tests were carried out at four different temperatures (-40/spl deg/C, 25/spl deg/C, 75/spl deg/C and 125/spl deg/C) and a range of stress levels. The constitutive equation for the steady-state creep law is reported. Low cycle fatigue behavior for 95.5Sn-3.8Ag-0.7Cu bulk solder specimens were investigated over a range of test temperatures (-40/spl deg/C, 25/spl deg/C, 75/spl deg/C and 125/spl deg/C) and frequencies (1 Hz, 0.01 Hz, and 0.001 Hz). Frequency modified strain-based and energy-based low cycle fatigue models are proposed for solder fatigue life prediction analysis.

Isothermal and thermal cycling aging on IMC growth rate in lead-free and lead-based solder interface

The growth of interfacial intermetallic compounds (IMC) between Pb-free and Pb-based solders with different surface finish (Cu and Ni/Au) metallization is a major concern for long-term solder joint reliability performance in electronic assemblies. The growth rate of the IMC layer can affect the solder joint reliability. Analysis of solid-state diffusion mechanism for the growth of IMC between solder-to-substrate interface for Pb-free and Pb-based solders subject to isothermal and thermal cycling aging were conducted. Experimental study of IMC layer growth between Sn3.8Ag0.7Cu and Ni/Au surface finish by isothermal aging versus thermal cycling (TC) aging was investigated to develop a framework for correlating IMC layer growth behavior. An integrated model for IMC growth was derived to describe the Ni-Cu-Sn IMC growth behavior subject to TC aging. Comparison of modeling and test results showed that IMC layer growth rate under TC aging was accelerated. It is noted that IMC layer growth study from various references showed different experimental data and growth kinetic parameters for both liquid-state and solid-state reactions.

Mechanical characterization in failure strength of silicon dice

The trend in die size decrease of the microelectronics circuits has been driven by modern IC manufacturing technology. Due to its brittle nature, high stresses induced in the die due to packaging, assembly and reliability test could result in detrimental fracture in the die. Due to its large diameter and thin layer, determination of the fracture strength of a silicon wafer would be difficult. Thus it is more applicable for silicon strength to be characterized at die level. This paper discusses the approach for the characterization of silicon die failure strength employing a simple three-point bending test, thereby providing a better understanding of the stress accumulated in the die before failure. The effects of die thickness, die size and backgrinding patterns on the die stress have been investigated. The results showed that the die strength is largely dependent on its geometry and damages due to wafer processes (surface/edge defects and backgrinding pattern). A set of thickness dependent threshold stress values for die failure has been obtained for wafers that have undergone mechanical grinding. The determined failure stress values would be useful for solving future die failure problems encountered in new packaging and process development work.

Design for reliability (DFR) methodology for electronic packaging assemblies

Design for reliability requires knowledge based in materials testing and modeling, finite element modeling and simulation, failure mechanism and life prediction and reliability tests for validation. A comprehensive mechanics characterization of electronic solders such as Sn/Pb and Pb-free solders has been established. Examples of conventional 2D and 3D Finite Element Analysis is provided for Thermal Cycling analysis of elastic-plastic-creep analysis of solder joints. The combined effect of modeling viscoelastic underfill and viscoplastic solder is reported for thermal cycling (TC) and thermal shock loading (TS). Two global-local modeling techniques for board-level analysis was calibrated. The global-local 3D modeling techniques are global-local submodeling (GLS) and global-local-beam (GLB) methods.

Lead free solder joint reliability characterization for PBGA, PQFP and TSSOP assemblies

In this study, thermal cycling test from -40/spl deg/C to 125/spl deg/C with 1 hour per cycle for Sn/sub -3.8/Ag/sub -0.7/Cu solder joint electronic assemblies was conducted for PBGA316, PQFP208, PQFP176, and TSSOP48 components. Two PCB surface finish conditions were investigated for ENIG and OSP. Daisy chain, in-situ resistance monitoring with data logger, was used for failure detection when the resistance value is larger than 300/spl Omega/. A two-parameter Weibull distribution model was used to determine the mean time to failure (MTTF) for different components. The Weibull parameters such as characteristic life and slope are compared for PBGA assembly with Ni/Au and OSP surface finishes. Microscopy was used to determine the crack path and failure mode. It was shown that components with Ni/Au surface finish have higher thermal fatigue life than those with OSP surface finish. PBGA solder joints are more sensitive to thermal fatigue failure than solder joints in PQFP and TSSOP components. More failures occur at the package side than board side for PBGA assembly. Fatigue life prediction was conducted using fatigue life prediction model and FEA analysis results for different component types. Quarter model with submodeling technique was used in FEA simulation due to symmetric geometry and uniform loading for PBGA, PQFP and TSSOP assemblies. Effect of solder joint location on fatigue life was studied based on FEA result for different assemblies. It was shown that test and predicted fatigue life results have a good agreement for different component types.

Isothermal and thermal cycling aging on IMC growth rate in Pb-free and Pb-based solder interfaces

The growth of interfacial intermetallic compounds (IMC) between Pb-free and Pb-based solders with different surface finish (Cu, Ni, Au metallizations) is one of the major concerns in long-term solder joint reliability performance in electronic assemblies. The growth rate of the IMC layer plays a major role on the life-time of the solder joints. As the diffusion and the reaction are thermally activated processes, the growth rate of the IMC layer is sensitive to temperature changes. Critical review and analysis of solid-state diffusion mechanism for the growth of IMC between solder-to-substrate interface for Pb-free and Pb-based solders subject to isothermal and thermal cycling aging is conducted. Through isothermal annealing the growth rate of the IMC layer at a given temperature and its general dependence on temperature can be determined by plotting the measured IMC layer thickness against time at iso-temperatures. However, real solder joints in electronic assemblies undergo thermal cycling due to environmental temperature changes and/or power on/off cycles. Therefore, data obtained by thermal cycling (TC) aging exposure is more practical in understanding IMC growth behavior in solder joints. However, in TC aging tests, the IMC growth rate is often determined also by plotting the measured IMC thickness against the accumulated time exposure (corresponding to the number of cycles of TC aging). This can lead to incorrect physics-of-failure characterization of IMC growth kinetics for TC aging effects, as IMC growth is temperature and time dependent and is expected to have thermally activated thresholds below which at a certain temperature no IMC growth is expected. Therefore, it is obvious that the whole TC cycle does not contribute to IMC growth and hence using accumulated time corresponding to TC cycle time is not justified. Hence, in this study, comparison between IMC layer thickness data by isothermal aging versus thermal cycling aging are used to develop a framework for correlating IMC layer growth behavior between isothermal and thermal cycling effects.

Vibration fatigue analysis for FCOB solder joints

Vibration fatigue tests and analysis for flip chip solder joint reliability assessments were investigated. Dynamic characterizations of flip chip on board (FCOB) assemblies were evaluated using accelerometer and high-speed camera measurements during vibration tests. Out-of-plane vibration fatigue tests were investigated for constant G-level tests at 3 G, 5 G and 10 G respectively. A varying G-level vibration test with 3 G, 5 G and 10 G blocks arranged in ascending sequence was conducted for cumulative fatigue damage assessment study. The test results for outer chains on the large chips satisfy the two-parameter Weibull distribution well. FEA using a global-local submodeling method was used to compute the fundamental frequency result, compared to experimental data. A quasi-static analysis method was developed to model the effect of flip chip location on solder joint fatigue life. The linear cumulative damage analysis method (Miners rule) predicted nonconservative results for vibration fatigue failures in the flip chip solder joints. Transient vibration behavior after drop test was also studied to predict the fatigue life of the FCOB assembly subjected to drop loading.

Mechanical failure strength characterization of silicon dice

Modem Integrated Circuit technology has driven the trend in die size and thickness decrease of the microelectronics circuits. High stresses induced in the die due to packaging, assembly and reliability tests begin to surface. Due to its brittle nature, moderate stresses could result in detrimental fracture in the die. However failure strength (stress) of the silicon die has not been readily available, and it is difficult to determine fracture strength of a silicon wafer because of its large diameter and thin layer which could break easily. Hence it would be meaningful for silicon strength to be characterized at die level. This paper discusses an approach for the characterization of silicon die failure strength, using a simple three-point bending method commonly used for brittle material testing. This helps to provide a better understanding of the stress accumulated in the die before failure. The effects of die thickness, die size and backgrinding patterns on the die stress have been investigated. The results revealed that die stress at failure actually increases with thinner die, indicating that a thinner die in a package can withstand higher load before failure. As anticipated, die with a thicker width can subject to greater stress before breakage, as higher load is needed to induce crack propagating through a larger grain boundary. Macroscopic analysis on the cracked die samples also revealed cleavage fracture and chevron patterns related to brittle fracture surfaces. It could be seen that threshold value for die strength is largely dependent on die size and die thickness. The threshold failure stress values would be useful for solving future die failure problems encountered in new packaging and process development work.

Lead-free 96.5Sn-3.5Ag flip chip solder joint reliability analysis

Lead-free 96.5Sn/3.5Ag flip chip solder joints were subjected to both thermal shock (-55/spl deg/C to 125/spl deg/C) and thermal cycling (-40/spl deg/C to 125/spl deg/C) reliability tests respectively. Two-parameter Weibull distribution plots, the Mean Time to Failure (MTTF) life are compared. Scanning electron microscopy (SEM) examination was performed on the cross-section surface of failed samples to observe the failure sites and modes. Finite element modeling and simulation of the thermal cycling and thermal shock tests were simulated. An elastic-plastic-creep analysis model was implemented to simulate time independent plasticity and time dependent creep deformations in the solder joints. Solder joint fatigue models were used for life prediction analysis employing the inelastic strain parameters derived from the finite element results.

Modeling plated copper interconnections in a bumpless flip chip package

The bumpless flip chip package (BFCP) is a novel integrated circuit (IC) package which employs an electrochemical process to form plated copper interconnections between the IC-to-substrate chip-level assembly. This unique packaging process does not require wire bonding or solder bumped flip chip interconnection procedures. The plated copper chip interconnection provides a robust connection, which is redistributed with nickel coated copper traces without an interposer substrate to compliant terminals in an area array package. The plated copper interconnections in the BFCP addresses reliability concerns by providing a stronger micro-joining alternative to wire bonding or flip chip soldering. The unique compliant redistribution design in the BFCP is expected to improve the solder joint reliability performance at board-level assembly. Package-level thermal cycling tests and analysis were conducted, along with finite element modeling and simulation of the BFCP subject to package-level temperature cycling.