T. Higuchi

A common data acquisition system for high-intensity beam experiments

The J-PARC facility, which will be ready in 2008, is being constructed to perform a number of experiments including nuclear physics, kaon decays and neutrino oscillation. The expected data acquisition rate ranges from 500 Hz to 10 kHz, which is significantly higher than those used in the existing small experiments at KEK. We have developed a new data acquisition system that can be used in a wide range of experiments at J-PARC. The system consists of a KEK-VME crate, a readout platform module and peripheral modules. The readout platform module is highly modularized, having four slots to install daughter cards for digitization and three PCI mezzanine card (PMC) slots for on-board data processing and other purposes. The performance of the platform module and a model setup of the data acquisition system are reported

Modular pipeline readout electronics for the SuperBelle drift chamber

In order to explore new physics in B-meson decays we plan to upgrade the KEK B-factory to a luminosity of 5/spl times/10/sup 35/ cm/sup -2/ s/sup -1/. In parallel we are developing a new pipelined data acquisition system for the Belle detector to cope with higher trigger rates of up to 30 kHz and severe background conditions. In order to reduce development and maintenance costs, we have adopted a modular design for these new readout electronics. The chosen architecture consists of a common readout platform, upon which are mounted subdetector specific parts, customized to meet the readout requirements of each sub detector component. As an example of this new architecture, we present in this paper the design of drift chamber electronics. The drift chamber readout utilizes the AMT-3 time-to-digital converter chip, originally developed for the ATLAS experiment, which satisfies the performance requirement for current and future Belle drift chamber readout. A data transfer performance test with emulation modules, mounted on the common platform, shows that the new readout electronics works well at a more than 30 kHz input trigger rate.

The silicon vertex detector for the super B factory

The silicon vertex detector (SVD2) of the Belle experiment at KEK (Tsukuba, Japan) is currently close to its limits in terms of the occupancy of the innermost layer and the readout dead time. In order to cope with further increase in luminosity, different levels of upgrades are proposed: small improvements are possible in the short term by tuning the current system at the cost of signal-to-noise and crosstalk. In 2007, the two inner layers of the SVD2 will be replaced by similar detectors with faster readout electronics (SVD2.5) and in the long term, a major upgrade of the full silicon vertex detector (SVD3) is envisaged for the KEK Super B Factory. These upgrade scenarios will be discussed in detail from the hardware point of view along with the options under study.

A common data acquisition system for high intensity beam experiments

The J-PARC facility, which will be ready in 2008, is being constructed to perform a number of experiments including nuclear physics, kaon decays and neutrino oscillation. The expected data acquisition rate ranges from 500 Hz to 10 kHz, which is significantly higher than those used in the existing small experiments at KEK. We have developed a new data acquisition system that can be used in a wide range of experiments at J-PARC. The system consists of a KEK-VME crate, a readout platform module and peripheral modules. The readout platform module is highly modularized, having four slots to install daughter cards for digitization and three PCI mezzanine card (PMC) slots for on-board data processing and other purposes. The performance of the platform module and a model setup of the data acquisition system are reported

Radiation tolerance of readout electronics for Belle II

We plan to start the Belle II experiment in 2015 and to continue data taking for more than ten years. Because some of the front-end electronics cards of Belle II are located inside the detector, radiation effects onto their components will be a severe problem. Using experimental exposure facilities of neutrons and ? rays, we study the radiation effects from these particles to the Virtex-5 FPGA, optical transceivers, and voltage regulators. The Virtex-5 FPGA is found to keep its operation after irradiation of more than 20-year-equivalent neutron flux of Belle II and 88-year-equivalent ?-ray dose. We observe single event upsets (SEUs) and multiple bit upsets (MBUs) in the Virtex-5 FPGA in the neutron irradiation. We also find almost doubled SEU counts in the Virtex-5 FPGA bombarded from its tail side than its head side. We extrapolate the observed SEU and MBU counts in the Virtex-5 FPGA to the entire readout system of the Belle II central drift chamber, and expect the SEU and MBU rates as one SEU per four minutes and one MBU per 11.5 hours, respectively. The optical transceivers are found to keep its operation after integration of 12-year-equivalent neutron flux, while they are killed by about 3-year-equivalent ?-ray dose, which should be solved in the future research. The voltage regulators are found to keep its operation for more than 10-year-equivalent ?-ray dose.

Performance of the AMT-3 based TDC system at Belle

The KEKB storage ring for a B-factory experiment at KEK, Japan, has been breaking the luminosity record of e+e- colliders. Now the luminosity reaches 1.6 times larger than the designed luminosity. The Belle detector at KEKB uses a traditional readout method based on the trigger and delay: almost all of the digitizer is the same FASTBUS TDC whose intrinsic deadtime is not negligible in a recent high luminosity condition. To accommodate more higher luminosity, we developed new pipelined TDC module and its intrinsic deadtime is smaller than 10% of the current TDC. We report the performance of this TDC module.

Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.

Belle II silicon vertex detector

The Belle II experiment at the SuperKEKB collider in Japan is designed to indirectly probe new physics using approximately 50 times the data recorded by its predecessor. An accurate determination of the decay-point position of subatomic particles such as beauty and charm hadrons as well as a precise measurement of low-momentum charged particles will play a key role in this pursuit. These will be accomplished by an inner tracking device comprising two layers of pixelated silicon detector and four layers of silicon vertex detector based on double-sided microstrip sensors. We describe herein the design, prototyping and construction efforts of the Belle-II silicon vertex detector.

The three-level event building system for the Belle II experiment

Belle II, an experiment designed to search for physics beyond the standard model in the decay of B mesons, will soon start operation at the Super KEKB e+ e- collider. The trigger rate is expected to be 30 kHz with a margin of 10 kHz, and the raw data rate will exceed 30 GB/s. Since the system will be unable to record all data on its storage system, online reduction is required. We have developed a three-level event building system using inexpensive switches and software for traffic smoothing, enabling online event processing at a reasonable cost. The data will be recorded on the storage system about 3 GB/s after rate reduction. This paper describes the architecture and the verification result in actual beam tests.

New Backend Processor Card for the Pipelined Readout System at Belle II

The Belle II experiment at the Super KEKB storage ring at KEK will search New Physics beyond the Standard Model, with 40 times higher luminosity than at KEKB. Much higher event rates are accounted for by moving all front-end digitizers inside or near the detector, and the resulting data received by a common pipeline readout platform developed in KEK. There are about 200 such platforms in the Belle II experiment. We have developed a new Intel Atom based processor card to handle the data and send it to the event building system in three steps. We fully utilize the PCI bus bandwidth and meet the high data rate requirement. In this report, we describe this processor card and the results from testing it in a realistic setup.