T. Liu

CDF level 2 trigger upgrade

We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.

A data formatter for the ATLAS Fast Tracker

The Fast TracKer (FTK) is an upgrade to the ATLAS level-2 trigger. The FTK system will reconstruct tracks using data from the inner Pixel and SCT silicon detector modules at trigger rates up to 100 kHz. We present an overview of the Data Formatter system, which is designed to remap, share and reformat the Pixel and SCT module data to match the geometry of the FTK trigger towers.

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Future particle physics experiments looking for rare processes will have no choice but to address the demanding challenges of fast pattern recognition in triggering as detector hit density becomes significantly higher due to the high luminosity required to produce the rare process. The authors propose to develop a 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) chip for HEP applications, to advance the state-of-the-art for pattern recognition and track reconstruction for fast triggering.

The SVT Bypass for a Forward Lepton wide coverage in the CDF Trigger

The silicon-vertex-trigger (SVT) [1,2] at CDF is made of two pipelined processors: the associative-memory, AM [3,4], finding low precision tracks (roads) and the track-fitter, TF, refining the track quality with high-precision fits. We propose to extend the SVT use, now mostly focused on B-physics, to high-PT physics as a tracker in the forward/backward region. The upgraded SVT structure is easily improved working on firmware, or connecting the existing general purpose FPGA-based SVT boards, named Pulsars, with other Pulsars in a lego-structure. In particular, SVT can easily extend the prompt-lepton acceptance providing silicon-only tracks where the drift-chamber coverage is poor or missing (pseudorapidity larger than 1). Since prompt-leptons from high-PT events do not require precise impact parameter measurement, we dont need to measure these tracks with the maximum silicon detector resolution. We enlarge the use of the AM, to detect tracks above a defined PT threshold. We propose a bypass that brings the new thin roads found by AM, directly to the level-2 CPUs. While the slower full-resolution path (TF) will have to digest the normal AM road production, four new Pulsars will deliver new roads from AM to L2-CPU. All the hardware exists, needs only to be assembled. We present the bypass architecture, the forward-track quality and their possible use in Higgs triggers. The system timing is estimated from simulation on real data and measurements on test stand.

Level-2 Calorimeter Trigger Upgrade at CDF

The CDF Run II level 2 calorimeter trigger is implemented in hardware and is based on a simple algorithm that was used in Run I. This system has worked well for Run II at low luminosity. As the Tevatron instantaneous luminosity increases, the limitation due to this simple algorithm starts to become clear. As a result, some of the most important jet and MET (missing ET) related triggers have large growth terms in cross section at higher luminosity. In this paper, we present an upgrade of the L2CAL system which makes the full calorimeter trigger tower information directly available to the level 2 decision CPU. This upgrade is based on the Pulsar, a general purpose VME board developed at CDF and already used for upgrading both the level 2 global decision crate and the level 2 silicon vertex tracking. The upgrade system allows more sophisticated algorithms to be implemented in software and both level 2 jets and MET can be made nearly equivalent to offline quality, thus significantly improving the performance and flexibility of the jet and MET related triggers. This is a natural expansion of the already-upgraded level 2 trigger system, and is a big step forward to improve the CDF triggering capability at level 2. This paper describes the design, the hardware and software implementation and the performance of the upgrade system.

The "Road Warrior" for the CDF online silicon vertex tracker

The Online Silicon Vertex Tracker (SVT) is a new trigger processor dedicated to the 2-D reconstruction of charged particle trajectories at Level 2 of the CDF trigger. The SVT links the digitized pulse heights found within the Silicon Vertex detector to the tracks reconstructed in the Central Outer Tracker by the Level 1 Fast Track finder. The SVT was recently modified in order to increase its efficiency. The new configuration uses all the Silicon Vertex detector layers. On the other hand the processing time has increased. This can be a problem at higher luminosities of the Tevatron. The Road Warrior is a new board that eliminates redundant track candidates before Track Fitting. It is based on the principle of the Associative Memory. The algorithm used is described in the paper, as well as the hardware implementation.