T. Mollenhauer

0.86-nm CET Gate Stacks With Epitaxial

In this letter, ultrathin gadolinium oxide (Gd2O3 ) high-k gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET=0.86 nm. The extracted dielectric constant is k=13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond

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We demonstrate an all-optical switch based on a waveguide-embedded 1D photonic crystal cavity fabricated in silicon-on-insulator technology. Light at the telecom wavelength is modulated at high-speed by control pulses in the near infrared, harnessing the plasma dispersion effect. The actual absorbed switching power required for a 3 dB modulation depth is measured to be as low as 6 fJ. While the switch-on time is on the order of a few picoseconds, the relaxation time is almost 500 ps and limited by the lifetime of the charge carriers.

High-

A planar nanophotonic Fabry-Perot-like resonator that can defy strong absorption of about 20 000 cm(-1) in the cavity material is demonstrated. Visible laser emission is observed from two silicon subwavelength-sized high index contrast gratings with embedded polymer gain material. The size of the laser is reduced by an order of magnitude compared to established designs based on photonic bandgap structures. As silicon constitutes the most common carrier for electronics, the cost-efficient integration of compact laser sources for visible wavelengths comes within reach.

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The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate stracture on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices.

Dielectrics and FUSI NiSi Metal Electrodes

The lasing properties of an optimized two-dimensional photonic crystal structure with an organic gain material are investigated. The feedback structure which is fabricated in a thin film of Ta2O5 increases both the index contrast from the gain material as well as the optical confinement. By combining first-order and second-order photonic crystal structures, losses occuring at the edge of the second order structure are dramatically reduced leading to a lower laser threshold and/or to a much smaller footprint of the laser.

Ultrafast all-optical modulator with femtojoule absorbed switching energy in silicon-on-insulator

The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, the output and transfer characteristics of 70 nm printed gate length pMOSFETs with 22 nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.

Ultracompact silicon/polymer laser with an absorption-insensitive nanophotonic resonator.

A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20nm (3σ). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.

Influence of channel width on n - and p -type nano-wire-MOSFETs on silicon on insulator substrate

A “gate first” silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10μm down to 40nm on a fully depleted 25nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxialhigh-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.

Organic mixed-order photonic crystal lasers with ultrasmall footprint

We report on leakage current mechanisms in epitaxial gadolinium oxide (Gd(2)O(3)) high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semi con doctor capacitors are gated with complementary-metal-oxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd(2)O(3) thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of Phi(T) = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction.

Subthreshold characteristics of p-type triple-gate MOSFETs

Electrically variable shallow junction metal–oxide–semiconductor field effect transistors on silicon on insulator have been fabricated to evaluate the suitability of fabrication processes on a nanoscale. In addition, the limits of scalability have been explored reducing gate lengths down to 12 nm. Specific attention has been paid to the overlay accuracy as required for the fabrication of these double gate structures. The superior quality of hydrogen silsesquioxane (HSQ) as electron beam resist and as mask material is demonstrated. The transistor fabricated exhibits extremely low leakage currents and relatively high on currents. The 8 orders of magnitude difference between the on and off states demonstrates conclusively large potentials for metal–oxide–semiconductor structures with critical dimensions in the 10 nm regime.