T. P. Ma

Current transport in metal/hafnium oxide/silicon structure

Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the energy band diagrams and current transport mechanisms for metal/HfO/sub 2//Si structures. In particular, we have obtained the following quantities that will be useful for modeling and simulation: i) HfO/sub 2//Si conduction band offset (or barrier height): 1.13 /spl plusmn/ 0.13 eV; ii) Pt/HfO/sub 2/ barrier height: /spl sim/ 2.48 eV; iii) Al/HfO/sub 2/ barrier height: /spl sim/ 1.28 eV; iv) electron effective mass in HfO/sub 2/: 0.1 m/sub o/, where m/sub o/ is the free electron mass and v) a trap level at 1.5 /spl plusmn/ 0.1 eV below the HfO/sub 2/ conduction band which contributes to Frenkel-Poole conduction.

Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.

Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si/sub 3/N/sub 4/) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si/sub 3/N/sub 4/ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

High-quality oxide/nitride/oxide gate insulator for GaN MIS structures

We report on a SiO/sub 2//Si/sub 3/N/sub 4//SiO/sub 2/ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450/spl deg/C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150/spl deg/C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs.

Ferroelectric Field Effect Transistors for Memory Applications

The non-volatile polarization of a ferroelectric is a promising candidate for digital memory applications. Ferroelectric capacitors have been successfully integrated with silicon electronics, where the polarization state is read out by a device based on a field effect transistor configuration. Coupling the ferroelectric polarization directly to the channel of a field effect transistor is a long-standing research topic that has been difficult to realize due to the properties of the ferroelectric and the nature of the interface between the ferroelectric and the conducting channel. Here, we report on the fabrication and characterization of two promising capacitor-less memory architectures.

Frenkel-Poole trap energy extraction of atomic layer deposited Al2O3 and HfxAlyO thin films

Frenkel-Poole (FP) trap energies of atomic layer deposited Al2O3 and HfxAlyO thin films with various Hf∕Al compositions have been extracted. Using a method based on the field and temperature dependence of FP conduction, intrinsic trap energies under zero electric field can be extrapolated. Results indicate that FP trap energies increase from 0.56to1.48eV when adding more and more Al to HfO2. The trap energy seems to be inversely proportional to the square of the dielectric constant of the film, suggesting that traps may originate from the same type of defect, whose energy level is mediated by the dielectric constant.

High performance gate first HfSiON dielectric satisfying 45nm node requirements

We show an ALD based HfSiON gate dielectric scaled to 1 nm EOT with excellent performance and reliability. Furthermore, the HfSiON dielectric films are integrated in a gate first approach that includes a 1000degC-5s anneal. It is also demonstrated that this 1 nm EOT HfSiON can achieve electron and hole mobilities comparable to that of SiON. This progress is enabled due to better understanding of the relationship between charge trapping, HfSiON thickness and crystallinity. Performance and reliability improvement is attributed to reduced charge trapping due to suppressed crystallization of the optimized HfSiON films

Temperature dependence of gate currents in thin Ta2O5 and TiO2 films

This letter reports our study of the temperature dependence of gate currents in thin Ta2O5 and TiO2 films. The study was conducted (1) to study the conduction mechanisms and band alignments, and (2) to determine whether the gate leakage current is tolerable at high temperatures for either of these high-dielectric-constant (high-k) oxides. The I–V characteristics of these oxides were measured and analyzed over a wide temperature range from 25 to 400u200a°C. Currents in Ta2O5 samples exhibited stronger temperature dependence than those in TiO2 samples, especially at high fields, mainly due to a much smaller electron barrier height of Ta2O5 over Si (0.28 eV) than that of TiO2 over Si (0.9 eV).

Ga2O3(Gd2O3)∕Si3N4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion

A dual-layer gate dielectric approach for application in III-V metal-oxide-semiconductor field-effect transistor (MOSFET) was studied by using ultrahigh vacuum deposited 7–8nm thick Ga2O3(Gd2O3) as the initial dielectric to unpin the surface Fermi level of In0.18Ga0.82As and then molecular-atomic deposition of ∼2–3nm thick Si3N4 as a second dielectric protecting Ga2O3(Gd2O3). The total equivalent oxide thickness achieved in this study is 5nm. We have demonstrated an enhancement mode In0.18Ga0.82As∕GaAs MOSFET with surface inverted n channel with drain current (Id) of 0.1mA for a gate length of 10μm and a gate width of 880μm at Vds=1V and Vg=4.5V.

Advanced Dual Metal Gate MOSFETs with High-k Dielectric for CMOS Application

This paper reports the fabrication of MOSFETs with dual metal gate electrodes. Low threshold voltage (Vt) was achieved using TaC for nFETs and MoNx for pFETs. The transistors show excellent Ion-Ioff performance with well-controlled short channel effects. Benefited from a novel approach in base oxide formation, high mobility at ~90% of poly/SiO2 was achieved on thick HfO2 (30A). Improvement in current drivability by the incorporation of conventional cap stressor was also presented. The data demonstrates one of the best MOSFETs to date with dual metal gates on high-k dielectrics. It is further observed that high-k crystallization induces Vt non-uniformity in small devices. To our knowledge, the impact of crystallization to high- k manufacturability is addressed here for the first time