T.R. Weatherford

Critical evaluation of the pulsed laser method for single event effects testing and fundamental studies

In this paper we present an evaluation of the pulsed laser as a technique for single events effects (SEE) testing. We explore in detail the important optical effects, such as laser beam propagation, surface reflection, and linear and nonlinear absorption, which determine the nature of laser-generated charge tracks in semiconductor materials. While there are differences in the structure of laser- and ion-generated charge tracks, we show that in many cases the pulsed laser remains an invaluable tool for SEE testing. Indeed, for several SEE applications, we show that the pulsed laser method represents a more practical approach than conventional accelerator-based methods. >

Single-event phenomena in GaAs devices and circuits

The single-event upset (SEU) characteristics of GaAs devices and circuits are reviewed. GaAs FET-based integrated circuits (ICs) are susceptible to upsets from both cosmic-ray heavy ions and protons trapped in the Earths radiation belts. The origin of the SEU sensitivity of GaAs ICs is discussed in terms of both device-level and circuit-level considerations. At the device level, efficient charge-enhancement mechanisms through which more charge can be collected than is deposited by the ion have a significant negative impact on the SEU characteristics of GaAs ICs. At the circuit level, different GaAs digital logic topologies exhibit different levels of sensitivity to SEU because of variations in parameters, including logic levels, capacitances, and the degree of gate or peripheral isolation. The operational and SEU characteristics of several different GaAs logic families are discussed. Recent advances in materials and processing that provide possible solutions to the SEU problem are addressed.

Heavy ion and proton analysis of a GaAs C-HIGFET SRAM

The authors present heavy-ion and proton upset measurements, including total dose and displacement damage, on a one-micron, GaAs, complementary-heterostructure insulated-gate FET (C-HIGFET) 1k*1k static random-access memory (SRAM). Single event upset (SEU) characteristics show a two-order-of-magnitude improvement over GaAs MESFET technology. Heavy-ion upset equilibrium measurements show that all cells upset with equal probability at the 5% linear energy transfer (LET) threshold. This indicates that for this device the shape of the cross section versus LET curve is a result of a probability distribution that applies to all cells and is not the result of variations in cell sensitivities. The data set also indicates that the traditional two-dimensional cos( theta ) normalization to LET and fluence is not applicable to this technology. >

Particle-induced mitigation of SEU sensitivity in high data rate GaAs HIGFET technologies

Proton and heavy ion data on two GaAs HIGFET logic families, one source coupled (SCFL) and the other complementary (C-HIGFET), show the importance of dynamic testing and develop a new technique for mitigating SEU sensitivity by minimizing charge enhancement effects.

Heavy ion SEU immunity of a GaAs complementary HIGFET circuit fabricated on a low temperature grown buffer layer

We compare dynamic SEU characteristics of GaAs complementary HIGFET devices fabricated on conventional semi-insulating substrates versus low temperature grown GaAs (LT GaAs) buffer layers. Heavy ion test results on shift register and flip-flop devices from the same process lot demonstrate that the LT GaAs layer provides immunity from upsets, even at an LET value of 90 MeV/spl middot/cm/sup 2//mg. This result is also consistent with pulsed laser measurements performed on the same flip-flop circuits used in the ion test.

Elimination of charge-enhancement effects in GaAs FETs with a low-temperature grown GaAs buffer layer

The use of a low temperature grown GaAs (LT GaAs) buffer layer in GaAs FETs is shown via computer simulation and experimental measurement to reduce ion-induced charge collection by two to three orders of magnitude. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the FETs. Error rate calculations indicate that the soft error rate of LT GaAs integrated circuits will be reduced by several orders of magnitude when compared to conventional FET-based GaAs ICs.

The shape of heavy ion upset cross section curves (SRAMs)

An expression for SEU (single event upset) cross section for a unidirectional, monoenergetic ion beam is developed. The expression incorporates both the stochastics of the energy deposition process and the variability of the response of an array of memory cells. The energy deposition stochastics result from the distribution of path lengths the ion may take through a memory cell and the statistics of the charge production process. The variability in the memory response results from the dependence of the sensitive volume size on deposited charge and cell-to-cell variations due to processing. Thus the shape of a measured upset cross section curve is the result of the complex interplay of a number of physical processes whose relative contributions vary with experimental conditions, memory technology, and processing. A procedure for the separation of the basic memory response from the stochastics of the energy deposition process using heavy ion SEU measurements is given. This can be used to predict the SEU vulnerability in any radiation environment. Results of the model applied to data for bipolar and CMOS/SOS SRAMs (static random-access memories) are presented. >

Charge-collection characteristics of GaAs heterostructure FETs fabricated with a low-temperature grown GaAs buffer layer

The charge-collection characteristics of GaAs heterojunction-insulated-gate FETs fabricated with a low-temperature grown GaAs (LT GaAs) buffer layer are investigated as a function of device bias conditions for laser and ion irradiation. In accordance with earlier measurements, the LT GaAs FETs of this study exhibit a significant reduction in charge-collection efficiencies when compared to those of conventional FETs. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the LT GaAs devices. It is revealed that charge-enhancement processes do occur in the LT devices under certain bias conditions, although at significantly reduced levels when compared to conventional FETs.

SEU rate prediction and measurement of GaAs SRAMs onboard the CRRES satellite

Upset rate predictions using heavy ion data are shown to overestimate the observed rates on CRRES (Combined Release and Radiation Effects Satellite) for the GaAs C-EJFET (complementary enhancement junctions FET) SRAM (static random-access memory) for both heavy ion and proton upset rates. The predicted heavy ion rates were an order of magnitude high, while the predicted proton upset rates were two orders of magnitude high. Predictions based on heavy ion data for the D-MESFET/resistor technology fell within an order of magnitude of the observed rate for both cosmic ray and proton upset rates. SPICE calculations underpredicted the upset rates for the C-EJFET SRAMs and overestimated the D-MESFET/resistor SRAM upset rates. The underestimate of comsic ray rates may be attributed to either a minimal assumption of collection depth or the possibility of enhanced charge collection. Incorrect use of the circuit-derived critical charge relative to the average measured critical charge would lead to the estimation of the heavy ion upset rate predictions for the D-MESFET/resistor SRAM. Observation of upset rates following onset of the solar flare event suggests that solar protons were responsible for high upset rates at the higher altitudes. >

Can digital GaAs be used in a space environment? A look at single event upset in GaAs

The vulnerability to SEU (single event upset) of devices produced by standard GaAs processes is too great to allow their use in space applications without some type of mitigation technique. GaAs foundries can provide solutions for the short term by providing SEU hardened designs incorporating redundancy for latches in standard cell families and gate arrays. As research progresses, techniques are expected to be found to reduce charge enhancement effects in GaAs FETs. Industry-developed solutions for sidegating and backgating effects may also improve SEU sensitivity. Designs intended for SEU environments can incorporate several mitigation techniques to provide satisfactory operation. However, hardening at the device may provide the best performance option.<<ETX>>