T. W. Sorsch

The electronic structure at the atomic scale of ultrathin gate oxides

The narrowest feature on present-day integrated circuits is the gate oxide—the thin dielectric layer that forms the basis of field-effect device structures. Silicon dioxide is the dielectric of choice and, if present miniaturization trends continue, the projected oxide thickness by 2012 will be less than one nanometre, or about five silicon atoms across. At least two of those five atoms will be at the silicon–oxide interfaces, and so will have very different electrical and optical properties from the desired bulk oxide, while constituting a significant fraction of the dielectric layer. Here we use electron-energy-loss spectroscopy in a scanning transmission electron microscope to measure the chemical composition and electronic structure, at the atomic scale, across gate oxides as thin as one nanometre. We are able to resolve the interfacial states that result from the spillover of the silicon conduction-band wavefunctions into the oxide. The spatial extent of these states places a fundamental limit of 0.7 nm (four silicon atoms across) on the thinnest usable silicon dioxide gate dielectric. And for present-day oxide growth techniques, interface roughness will raise this limit to 1.2 nm.

Multi-component high-K gate dielectrics for the silicon industry

Abstract The exponential growth of the silicon industry can be attributed to that fact that silicon has a native oxide that is silicon dioxide. With SiO 2 soon approaching its fundamental limit, we must find an alternate to SiO 2 or a new switch to replace MOSFETs. In this paper we focus on the leading alternate gate dielectrics. We first discuss the selection criteria for alternate gate dielectrics and why it is important to have an amorphous gate dielectric. SiO 2 and aluminum oxide remain amorphous at very high temperatures. For dielectrics with K >15 and gate power 2 , it may be necessary to stabilize the amorphous phase of metal oxides by adding Al or Si to the oxide, thus forming multi-component dielectrics such as aluminates. We then benchmark aluminates with aluminum oxide and silicon dioxide.

Nanopores in solid-state membranes engineered for single molecule detection

A nanopore is an analytical tool with single molecule sensitivity. For detection, a nanopore relies on the electrical signal that develops when a molecule translocates through it. However, the detection sensitivity can be adversely affected by noise and the frequency response. Here, we report measurements of the frequency and noise performance of nanopores </=8 nm in diameter in membranes compatible with semiconductor processing. We find that both the high frequency and noise performance are compromised by parasitic capacitances. From the frequency response we extract the parameters of lumped element models motivated by the physical structure that elucidates the parasitics, and then we explore four strategies for improving the electrical performance. We reduce the parasitic membrane capacitances using: (1) thick Si(3)N(4) membranes; (2) miniaturized composite membranes consisting of Si(3)N(4) and polyimide; (3) miniaturized membranes formed from metal-oxide-semiconductor (MOS) capacitors; and (4) capacitance compensation through external circuitry, which has been used successfully for patch clamping. While capacitance compensation provides a vast improvement in the high frequency performance, mitigation of the parasitic capacitance through miniaturization offers the most promising route to high fidelity electrical discrimination of single molecules.

Understanding the limits of ultrathin SiO 2 and Si-O-N gate dielectrics for sub-50 nm CMOS

Abstract In spite of its many attributes such as nativity to silicon, low interfacial defect density, high melting point, large energy gap, high resistivity, and good dielectric strength, SiO 2 suffers from one disadvantage, low dielectric constant (K=3.9). Thus, ultrathin SiO 2 gate dielectric layers are required to generate the high capacitance and drive current required of sub-50 nm transistors. The silicon industry roadmap dictates 4 nm SiO 2 gate dielectrics for 0.25 μm technology today, and calls for 2 thickness for 0.05 μm technology in 2012. SiO 2 layers in this thickness range may suffer from boron penetration, reduced drive current, reliability degradation, and high gate leakage current. We will argue that none of these problems are limitations for thicknesses greater than about 1.3 nm. Below that thickness, the fundamental problems of high tunneling current and reduced current drive will prevent further scaling, unless alternate gate dielectrics are introduced.

OXIDATION OF SI BENEATH THIN SIO2 LAYERS DURING EXPOSURE TO HBR/O2 PLASMAS, INVESTIGATED BY VACUUM TRANSFER X-RAY PHOTOELECTRON SPECTROSCOPY

Thin SiO2 layers were exposed to an HBr/O2 plasma for a variety of short periods, reproducing the over-etching process after polycrystalline Si gate electrodes have been etched and the gate oxide layer is exposed. Samples were transferred under vacuum to an x-ray photoelectron spectrometer for analysis. After relatively thick (>60 A) films were exposed to a 10% O2/HBr plasma at an average ion energy of ∼150 eV, the near-surface region becomes brominated, and the thickness of the film decreases, indicating an etching rate of ∼1–2 A/s. When the starting film thickness is between 10 and 20 A, however, exposure to the plasma results in an increases in the thickness of the film, and is enhanced with the increasing addition of oxygen to the feed gas. At mean ion energies of 40 or 150 eV, the transition from etching to deposition occurs at oxygen additions of ∼1% or ∼8%, respectively. The increase in SiO2 thickness is ascribed mainly to oxidation of the Si at the oxide-substrate interface, and not to deposition ...

The relentless march of the MOSFET gate oxide thickness to zero

Abstract The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.

Ultra-thin gate oxide reliability projections

Abstract We describe the reliability projection methods currently used and show that 1.6 nm oxides are sufficiently reliable even if soft breakdown is considered the point of failure. We also explore the possibility of using oxides after soft breakdown.

Gate Technology Issues for Silicon Mos Nanotransistors

This article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm