T.W. Sorsch

The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length

We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and (2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per /spl mu/m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L/sub G/) have been demonstrated without advanced lithography.

Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs

Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsat//spl ap/1.8 mA//spl mu/m can be achieved with a 60 nm gate at 1.5 V using a 1.3-1.4 nm gate oxide with a gate leakage current less than 20 nA//spl mu/m/sup 2/. Furthermore, we find that I/sub Dsat/ deteriorates for gate oxides thicker or thinner than this.

The ballistic nano-transistor

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel length nMOSFETs. The peak drive performance in an nMOSFET was observed at t/sub ox//spl ap/1.3 nm for a 1.5 V power supply voltage with T/sub n//spl ap/0.7, while the peak performance in a pMOSFET was observed at t/sub ox//spl ap/1.5 nm for a -1.5 V supply with T/sub p//spl ap/0.5. Since the carrier scattering in the channel is due predominately to interface roughness, reducing the transverse surface field, either by reducing the gate voltage or by increasing the oxide thickness, can be used to improve the transmittance T/sub n//spl rarr/0.85, T/sub p//spl rarr/0.6, while diminishing the drive current.

Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

To sustain the silicon CMOS scaling beyond 100 nm, an alternate gate dielectric with K>7 is needed. The deposited high K dielectrics (metal oxides) have nonstoichiometric composition and therefore have large electrical defects (traps) in the bulk of the dielectric and at the dielectric/semiconductor interface. In this paper, we report a novel doping method to quench traps in thin films of Al/sub 2/O/sub 3/ (K>8). By adding small amounts of dopants such as Zirconium (Zr) or Silicon (Si), we have achieved /spl sim/10nm thick aluminum oxide films with record low leakage current (<10/sup -13/A/mm/sup 2/) and ultra-thin (3-5 nm) aluminum oxide films with 2 very low interface state density (/spl sim/10/sup 10//cm/sup 2/-eV) at the silicon/aluminum oxide interface. We propose a physics based model for the doping effect and selection of dopants for metal oxides with K>10.

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates. These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology. In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20. With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/1.2 nm with leakage current <50 mA/cm/sup 2/ and gate power budget <50 mW/cm/sup 2/, at IV. For high performance, low power CMOS, beyond SiO/sub 2/, doped-aluminum oxide (with K/spl sim/10) may be a viable alternate gate dielectric. Beyond aluminum oxide, aluminates (with K>15) may be viable alternate gate dielectrics.

50 nm Vertical Replacement-Gate (VRG) pMOSFETs

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (<20 /spl Aring/) gate oxide.

Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradation

In this paper we report data on NMOS devices with ultra thin oxide (t/sub ox/=2 nm) and heavily doped substrates, showing, for the first time, that the gate current, for very low biases (-|V/sub FB/|<V/sub G/<0) cannot be explained by direct tunneling, but features an additional component which we attribute to gate electron tunneling into the anode interface states. Comparing measurements with simulations it is shown that this extra current can be used to estimate the interface states (D/sub it/) and to monitor oxide degradation in ultra thin oxides where the traditional stress induced leakage current due to bulk traps (SILC) is not detectable.

Progress toward 10 nm CMOS devices

One of the primary means for improving performance and increasing the scale of integration on a chip is the miniaturization of the electronic devices that comprise it. The SIA roadmap projects that future gains in performance will continue to accrue from this approach. One of the guiding principles for miniaturization has been the scaling of successful existing device designs to smaller dimensions. While there may be no compelling reason why the SIA targets cannot be achieved by continued scaling, an accurate assessment of the limiting performance that can be derived from conventional CMOS is crucial for identifying the principal impediments and for developing alternatives. Here, we identify five impediments that we have encountered as we attempt to scale CMOS technology toward 10 nm gate lengths: optical lithography, gate oxide tunneling, enhanced boron diffusion in the ultra-shallow junction, drive current saturation with decreasing oxide thickness, and the subthreshold current.

Monolithic fringe-field-activated crystalline silicon tilting-mirror devices

A new approach is presented for fabricating monolithic crystalline silicon tilting-mirror microoptoelectromechanical systems (MOEMS) devices. The activation electrodes, etched from a thick silicon layer deposited over insulating oxide onto the top surface of a silicon-on-insulator (SOI) wafer, are displaced from the mirrors and interact with these tilting elements via electrostatic fringing fields. In contrast to the more usual parallel-plate activation, the rotation angle saturates at high voltages. This paper discusses concept, design, and processing, and also compares modeling and measured performance of a specific 9/spl deg/ tilt range device array.

Spatial light modulator for maskless optical projection lithography

Spatial light modulators (SLMs) designed to replace photomasks for optical lithography have been designed, fabricated, and tested. These microelectromechanical devices are fabricated with alternating polycrystalline Si and sacrificial SiO2 layers that are patterned by a 193nm wavelength scanner to dimensions as small as 150nm. Aerial image simulations were used to define the mechanical requirements of the devices. Piston motion of electrically actuated devices was measured with an optical profilometer. The measurements were fit to a simple equation to within 1nm precision, which is adequate for defining 50nm features lithographically. Transient response measurements show that one version of the SLM responds to actuation as quickly as 20μs, fast enough for current 193nm wavelength excimer laser sources.