Tadashi Ae

Availability of k-coterie

The distributed k-mutual-exclusion problem (k-mutex problem) is the problem of guaranteeing that at most k processes at a time can enter a critical section at a time in a distribution system. A method proposed for the solution of the distributed mutual exclusion problem (i.e., 1-mutex problem) by D. Barbara and H. Garcia-Molina (1987) is an extension of majority consensus and uses coteries. The goodness of coterie-based 1-mutex algorithm strongly depends on the availability of coterie, and it has been shown that majority coterie is optimal in this sense, provided that: the network topology is a complete graph, the links never fail, and p, the reliability of the process, is at least 1/2. The concept of a k-coterie, an extension of a coterie, is introduced for solving the k-mutex problem, and lower and upper bounds are derived on the reliability p for k-majority coterie, a natural extension of majority coterie, to be optimal, under conditions (1)-(3). For example, when k=3, p must be greater than 0.994 for k-majority coterie to be optimal. >

A distributed k -mutual exclusion algorithm using k -coterie

Abstract The concept of k-coterie is introduced and a distributed k-mutual exclusion algorithm is proposed using it. A k-coterie is a natural extension of a coterie. The message complexity of the algorithm is O(c) when conflicts with other processes in capturing a quorum do not occur, where c is the maximum quorum size of the k-coterie the algorithm uses.

Distributed k-Mutual Exclusion Problem and k-Coteries

The distributed k-mutual exclusion problem is the problem of guaranteeing that at most k processes are in a critical section simultaneously. This problem can be solved using the k-coterie: We first prepare a set (k-coterie) C of sets (quorums) Q of processes such that each k-set {Q1,⋯, Qk} of quorums in C contains a pair Qi and Qj (i≠j) intersecting each other. A process wishing to enter a critical section is required to collect a permission from each member of a quorum in C. Then at most k processes can be in a critical section because of the intersection property of k-coterie, and the (average) number of messages necessary for entering a critical section is in proportion to the (average) quorum size of C.

On the removal of forbidden graphs by edge-deletion or by edge-contraction

Abstract If π is a property on graphs, the corresponding edge deletion (edge contraction, respectively) problem is: Given a graph G , determine the minimum number of edges of G whose deletion (contraction) results in a graph satisfying property π. We show that these problems are NP-hard if π is finitely characterizable by 3-connected graphs.

On the NP-hardness of edge-deletion and -contraction problems

Abstract If π is a property on graphs, the corresponding edge deletion (edge contraction, respectively) problem is: Given a graph G , determine the minimum number of edges of G whose deletion (contraction) results in a graph satisfying property π. We show that these problems are NP-hard if π is finitely characterizable by 3-connected graphs.

One-way simple multihead finite automata

Abstract The first half of this paper investigates the accepting powers of various types of simple one-way multihead finite automata. It is shown that (1)for each k ⩾1, simple one-way ( k +1)-head finite automata are more powerful than simple one-way k -head finite automata. (2)for each k ⩾2, nondeterministic simple one-way k -head finite automata are more powerful than deterministic ones, and (3)for each k ⩾2, sensing simple one-way k -head finite automata are more powerful than non-sensing ones. In the latter half, closure properties for various types of simple one-way multihead finite automata are investigated. Finally, we demonstrate that languages accepted by nondeterministic sensing simple one-way 2-head finite automata are related to some open problem concerning deterministic and nondeterministic tape-bounded Turing computations.

Programmable real-time scheduler using a neurocomputer

In real-time systems, the scheduling plays an important role to carry out all tasks within predefined time frames. The scheduling problem, however, is known to be intractable, that is, NP-hard or NP-complete for most cases (Garey and Johnson 1979). In this paper, one of the neural computation techniques is introduced to solve it within a limited time under the hard real-time environment, instead of improving algorithms on conventional computers. Although the neural computation can be realized on a multiprocessor, a special hardware using neural networks is designed to obtain the schedule results without overhead.

Optically Interconnected Kohonen Net for Pattern Recognition

The test chip of optically interconnected Kohonen net which realizes the parallel pattern recognition was designed and fabricated. The optical waveguides, micromirrors and photodiodes were integrated on a Si wafer and complementary metal oxide semiconductor (CMOS) chips were bonded on the same Si wafer. The optical input data are distributed to the CMOS circuits by the branched waveguide and the distances between the input and the reference data are calculated. This test circuit operated at a frequency of 6.7 MHz.

A template matching algorithm using optically-connected 3-D VLSI architecture

Three-dimensional VLSI (in short, 3-D VLSI) is a new device technology that is expected to realize high performance systems. In this paper, we propose an image processing architecture based on 3-D VLSI consisting of optically-connected layers. Since the optical inter-layer connection seems to have some of useful functions due to isotropic radiation of the light, we algebraicly formulate them as the picture processing operators. Moreover, we show that the operators are available for applications such as template matching. The availability of a proposed template matching algorithm is verified by simulation.

Real-time multimedia data processing using VLIW hardware stack processor

We propose the real-time processing of multimedia data using a special purpose processor. We introduce a VLIW architecture and a hardware stack for our multimedia processor. The VLIW-Hardware Stack Processor (VLIW-HSP) consists of four hardware stack units and one control unit. We discuss real-time multimedia data processing using the VLIW architecture. We show the design of VLIW-HSP and present several performance evaluations using a software simulation of VLIW-HSP. The results of these evaluations indicate that the hardware stack typically achieves a 20% speed improvement. We describe a hardware emulator for VLIW-HSP using an Xilinx FPGA which is necessary for application level performance evaluation.