Tadashi Otaka

Zero-shrink dimension evaluated for ArF-resist patterns measured by CD-SEM

Resist patterns for ArF-laser lithography slim by electron radiation in Critical Dimension-Scanning Electron Microscope (CD-SEM). To estimate initial CD that includes no LWS, the CD at 0th measurement was extrapolated from shrink-curve that indicates the slimming. Invisible slimming, occurring between the 0th and 1st measurement, was estimated. We made software for CD-SEM to calculate the 0th-CD. Estimation error in the extrapolated 0th-CD was estimated less than 0.9 nm, and the overall slimming including the invisible shrink was 0.3 nm in line-shaped patterns.

Observation of subsurface structures using high-energy SEM

Manufacturing integrated devices with faster clock speeds requires the fine control of three-dimensional gate structures, including line-edge roughness, sidewall angles, and sidewall structures, as well as the control of line widths. In addition, a way to observe underlying structures in devices with multi-layer interconnects is required. As a way to meet future metrology requirements, we propose the use of high-energy scanning electron micrscopy (SEM), which is better suited to the measurement of 3-D structures and underlying structures than conventional low-energy SEM. High-energy SEM is shown to reveal subsurface structures that are not detected by low-energy SEM. Firstly, a motched gate structure and a polycide gate with a sidewall spacer are observed with spatial resolutions of a few nanometers. The relationship between the thickness of the upper layer and beam energy at which underlying structures are observable is also investigated. The beam should be energetic enough to pass through the upper layer without being broadened, but weak enough that incident electrons are back-scattered by the underlying structures. We were able to observe line structures at depths of up to 800 nm by using incident beams with energy levels from 50 to 100 keV.

Effect of various ArF resist shrinkage amplitudes on CD bias

The beam parameters of CD SEM, accelerating voltage, beam current, measurement time, frame number, and magnification are evaluated to get the optimal setting for reducing the shrinkage of ArF resist. We check image resolution, resist shrinkage amplitude, CD bias between resist line and etched pattern to valuate the impact of beam parameters. On image resolution, the poly film is better resolved with the 800 V accelerating voltage. On the other hand, 300 V is more suitable for resist image. It also produces much lower resist shrinkage compared with 800 V. Beam current, measurement time, frame number, and magnification produce much less impact on resist shrinkage than the accelerating voltage. On CD bias, we also found that 300 V produces better accuracy and stability compared to 800 V. This is attributed to the lower resist shrinkage. Finally, we suggest an important concept that the optimal beam condition cannot be judged only by precision and resolution but also by the resist shrinkage and CD bias stability.

Nanometer-level metrology with a low-voltage CD SEM

This paper describes the application of a low-voltage scanning electron microscope (SEM) with nanometer-level accuracy for measurement in ultra-large-scale integration (ULSI). Minimum feature sizes of integrated circuits are expected to reach the 100-nm level and below (the nanometer region) in the near future. For the lithography process under that regime, precise critical dimension (CD) control and high resolution of resist patterns will be quite important for device fabrication, because variations in pattern sizes will degrade circuit performance. Therefore, metrology with nanometer-level accuracy is required for device fabrication under the regime. Here, we report on a CD-SEM that operates at 500 V to measure patterns at the 1 Gbit level. We used the S-8840 (Hitachi) to measure holes, lines/spaces, and the calibration standard (Micro-Scale). Several voltages from 500 V to 1000 V were used for the measurements. Static variation of less than 3 nm (3(sigma) ) was obtained in the pitch measurement of the Micro- Scale regardless of the acceleration voltages. For the holes, a lower voltage provided higher accuracy in static measurements. In the nanometer region, resist-pattern sizes microscopically fluctuate to the level of 10 nm due to the polymer characteristics of the resists (nano edge roughness). We could also characterize resist-pattern fluctuations with high accuracy. We compared our measurements with those from an atomic force microscope (AFM) for nanometer-level metrology, and conclude that at present CD-SEMs are more advantageous because of their higher accuracy and throughput.

Prospects for using primary electron-based CD metrology

CD SEM’s used for CD Metrology in semiconductor fabs rely upon secondary electron emission to indirectly image features on process wafers. The use of secondary electrons by current CD SEM technology limits the resolution of this metrology and hinders its ability to meet future requirements. An idea that has garnered some interest from both the research and commercial sectors is to use backscattered, or primary, electrons with very low energy losses to image patterned features directly. Such a device would operate with acceleration (and landing) potentials in the range of 50 keV-200 keV. One concern is whether the high energy incident electrons will damage active devices. It has been hypothesized that the substrate’s reduced stopping power for high energy electrons will result in the majority of the electron energy being deposited far below the device structures. We have explored the issue of device damage from high energy and high dose incident electrons and find that this technique results in unacceptable transistor degradation at all of the doses and landing energies explored. We present our findings in this paper.

Quantification of CD-SEM wafer global charging effect on CD and CD uniformity of 193-nm lithography

For 90 nm technology and below, we need to fight for every nanometer to improve the CD uniformity (CDU). New materials, especially for low-k material, bring about not only complicated integration challenges, but also new metrology difficulties such as SEM image focus failure if using low landing energy (300V) on charging wafer (e.g. -300V). The wafer global charging will also distort the CD SEM magnification and result in CD measurement error. CD SEM venders propose that the distortion be corrected by voltage contrast focus. In order to compare and quantify the measurement error correction with and without using retarding voltage focus, ArF resist non-uniform charging wafers (~ -300V) and low charging wafers (~ -7V) were prepared. Low landing energy like 300V is one of the solutions for ArF resist shrinkage. However, as the low landing energy (300V) meets the high global charging wafer (-300V), SEM cannot get sufficient secondary electron signal to construct image. Therefore, two landing voltages 500eV and 800eV were chosen for the evaluation. Three pitches 1600 nm, 460 nm and 230 nm were investigated. Two indexes are used to evaluate the wafer global charging effect on CD and CDU. One is within-wafer pitch uniformity for determining the CD SEM magnification error. The other is ArF-resist-shrinkage amplitude used to estimate the effective landing energy at charging area. The experimental results show that the pitch uniformity difference with and without using retarding focus can be larger than 2.5 nm. Similar phenomenon is also found for the line width uniformity. Resist shrinkage amplitude is significantly reduced at the highly charged area. Both results show that accurate focus procedure, i.e. retarding voltage focus employing first, is the key to reduce the CD metrology tool measurement error and improve CDU.

High-energy scanning electron microscope for the observation of subsurface structures

We propose a technique using high-energy scanning electron microscope (SEM), which has the advantage of measuring 3-D structures and underlayer structures when compared to conventional low-energy SEM, to meet future metrology requirements. At first, we demonstrate that a technique using high-energy SEM has the advantages of measuring gate structures with a spatial resolution of a few nanometers. For example, a notched gate structure was most clearly visible when the beam energy is at 200 keV. Another example of a polyside gate with a sidewall spacer was most clearly visible at 100 keV. In addition, we studied the relationship between the thickness of the upper layer and beam energy at which the structure of the underlayers can be observed. The beam energy should be high enough to pass through the upper layer without the incident beam becoming broader, but low enough for the incident electrons to be backscattered at the structures in the underlayer. We could observe the line structures at a depth of 800 nm or less using an incident beam with energy from 50 to 100 keV.