Tae-Sung Oh

Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

For high density and performance of microelectronic devices, the 3-D system in package (SiP) has been considered as a superb microelectronic packaging system. The development and evaluation of stacked chip type 3-D SiP with vertically interconnected TSV are reported. The process includes; 55 mum-diameter via holes by reactive ion etching (RIE), SiO2 dielectric layer by thermal oxidation, Ta and Cu seed layers by ionized metal plasma (IMP), Cu via filling by electroplating, Cu/Sn bump for multi-chip stacking and finally chip-to-PCB bonding with Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3-D SiP with 10 stacked chips was successfully fabricated. High frequency electrical model of the TSV was proposed and the model parameters were extracted from the measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. And then, contact resistances of Cu via and bump joint were discussed.

High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

In this paper, we firstly propose the high frequency equivalent circuit model of the chip-to-chip vertical via based on its physical configuration. The model parameters are extracted from the measurement of S-parameters using a vector network analyzer up to 20GHz frequency range. The proposed circuit model is verified experimentally in frequency and time domains. Furthermore, the high frequency characteristics of the chip-to-chip vertical via are investigated.

Suppression of Power/Ground Inductive Impedance and Simultaneous Switching Noise Using Silicon Through-Via in a 3-D Stacked Chip Package

We have thoroughly investigated the advantages of a silicon through-via (STV) interconnection in decreasing the inductive impedance of a power distribution network (PDN) and suppressing simultaneous switching noise (SSN) in a 3-D stacked chip package. A double-stacked chip package with STV interconnections was fabricated and measured together with a similar double-stacked chip package with conventional bonding-wire interconnections. We successfully demonstrated that significant reduction of the inductive PDN impedance, from 1.66 nH to 0.79 nH, can be achieved by replacing the conventional bonding wires in the multiple-stacked chip package by STV interconnections. Furthermore, we have shown that the STV interconnections can considerably reduce high-frequency SSN, by more than 80%, compared to the conventional bonding-wire interconnections.

Electrical Characteristics of the Pt/SrBi2.4Ta2O9/ZrO2/Si Structure for Metal–Ferroelectric-Insulator–Semiconductor Field-Effect-Transistor Application

The Pt/SBT/ZrO2/Si structure was proposed for metal–ferroelectric-insulator–semiconductor field-effect-transistor applications. A SrBi2.4Ta2O9 (SBT) thin film was prepared using liquid source misted chemical deposition (LSMCD) on a Si substrate with ZrO2 buffer layer deposited by reactive sputtering. The LSMCD-derived SBT film exhibited 2Pr of 16.6 µC/cm2 and Ec of 25 kV/cm at ±5 V. Interdiffusion between SBT and Si was suppressed with a ZrO2 layer thicker than 20 nm. The memory window of the Pt/SBT (400 nm)/ZrO2/Si with 20–50 nm ZrO2 became larger with increasing the gate voltage and decreasing ZrO2 thickness. The Pt/SBT (400 nm)/ZrO2 (20 nm)/Si exhibited memory windows of 0.83 V at ±5 V and 1.26 V at ±7 V.

Low Temperature and Ultra Fine Pitch Joints Using Non-Conductive Adhesive for Flip Chip Technology

The low temperature and ultra fine pitch chip on glass (COG) bonding using non-conductive adhesive (NCA) was developed. 30 mum pitch Sn bumps on Si chip were bonded with the metal pads on the glass substrate at 80 degC. Reflowed Sn bumps were used to reduce the NCA trapping. The initial contact resistance of the bump joints at 80 MPa pressure was less than 30 mOmega, which was lower than that of the joints using anisotropy conductive film (ACF). Aging treatment at 85 degC slightly decreased the contact resistance. Failed COG joints were not observed before and after aging

Fabrication and Evaluation of 3D Packages with Through Hole Via

System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50um-diameter via holes, conformal deposition of SiO 2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3D SiP stacked up to 10 layers was successfully fabricated. A high frequency electrical model of the through hole via was proposed and the model parameters were extracted from measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Contact resistances of Cu via and bump joint were presented.

Electrical characteristics of SrxBi2.4Ta2O9 thin film and Pt/Sr0.85Bi2.4Ta2O9/Al2O3/Si structure

SrxBi2.4Ta2O9 (0.7 ≤ x ≤ 1.3) thin films were processed by metalorganic decomposition and their ferroelectric characteristics were investigated. The Sr-deficient SrxBi2.4Ta2O9 films exhibited well-developed ferroelectric hysteresis curves compared to those of the Sr-excess films, and Sr0.85Bi2.4Ta2O9 film had the optimum electrical characteristics among SrxBi2.4Ta2O9 films. Electrical characteristics of the Pt/SBT/Al2O3/Si structure using Sr0.85Bi2.4Ta2O9(SBT) film were investigated for metalferroelectric-insulator-semiconductor field-effect-transistor (MFIS-FET) applications. Memory window of C-V hysteresis characteristics of the Pt/SBT/Al2O3/Si structure became large with decreasing the Al2O3 thickness, and the Pt/SBT(400 nm)/Al2O3 (10 nm)/Si structure gave memory window of 2.2 V at sweeping voltages of ±5 V. The Pt/SBT/Al2O3/Si structure can be proposed for MFIS-FET applications.

Dielectric Properties and Leakage Current Characteristics of Al 2 O 3 Thin Films with Thickness Variation

Dielectric properties and leakage current characteristics of the Al 2 O 3 thin films, deposited by reactive sputtering at room temperature, have been investigated with variations of the O 2 content in the sputtering gas and the film thickness. The Al 2 O 3 films of 10-300 nm thickness were amorphous without depending on the O 2 contents of 25-75% in the sputtering gas. Maximum dielectric constant was obtained for the Al 2 O 3 film deposited with the sputtering gas of 50% O 2 content. With reduction of the film thickness from 300 nm to 10 nm, dielectric constant decreased from 9.04 to 3.71 and tangent loss increased from 0.0035 to 0.0594, respectively. When the O 2 content in the sputtering gas was higher than 50%, the Al 2 O 3 films exhibited no shift of the flatband voltage in C-V curves. The leakage current density increased with increasing the film thickness, and the Al 2 O 3 films thinner than 100 nm exhibited the leakage current densities lower than 10 −6 A/cm up to 650 kV/cm.

Characteristics of Pt/SBT/Al 2 O 3 /Si Structures for MFIS-FET Applications

Pt/Sr 0.85 Bi 2.4 Ta 2 O 9 /Al 2 O 3 /Si structures were prepared for MFIS-FET applications. After depositing Al 2 O 3 film of 10-50 nm thickness by reactive sputtering on Si(100) substrate as a buffer layer, Sr 0.85 Bi 2.4 Ta 2 O 9 (SBT) thin film of 400 nm thickness was prepared onto it by metalorganic decomposition process. With annealing at 800°C for 1 hour in oxygen ambient, the 400 nm-thick SBT film exhibited 2P r of 10.2 μC/cm 2 and E c of 37.5 kV/cm at ±5V. C-V characteristics of the Pt/SBT/Al 2 O 3 /Si structures exhibited hysteresis loops due to the ferroelectric switching behavior of the SBT film. When the Al 2 O 3 buffer layer was thicker than 10 nm, the memory window and maximum capacitance of the Pt/SBT/Al 2 O 3 /Si structure increased with decreasing the thickness of the Al 2 O 3 buffer layer, and the Pt/SBT(400 nm)/Al 2 O 3 (10 nm)/Si structure exhibited a memory window of 2.2 V at ±5 V.