Taehyung Kim

Network massive MIMO for cell-boundary users: From a precoding normalization perspective

In this paper, we propose network massive multiple-input multiple-output (MIMO) systems, where three radio units (RUs) connected via one digital unit (DU) support multiple user equipments (UEs) at a cell-boundary through the same radio resource, i.e., the same frequency/time band. For precoding designs, zero-forcing (ZF) and matched filter (MF) with vector or matrix normalization are considered. We also derive the formulae of the lower and upper bounds of the achievable sum rate for each precoding. Based on our analytical results, we observe that vector normalization is better for ZF while matrix normalization is better for MF. Given antenna configurations, we also derive the optimal switching point as a function of the number of active users in a network. Numerical simulations confirm our analytical results.

A wireless fair scheduling algorithm for 1/spl times/EV-DO system

A 1/spl times/EV-DO system adopts the dynamic data rate transmission technique to support an efficient data service with proportional fairness scheduler. Proportional fairness guarantees good throughput and channel sharing fairness but it does not address the fair scheduling of delay sensitive packet flows. We propose WFQ-PF which is composed of WFQ (weighted fair queuing) and a wireless fair packet service scheduler based on proportional fairness. Preliminary results on the proposed scheduler are given and we notice that this algorithm is an effective control on packet delay which is caused by location-dependent low throughput of a user.

Asymptotic Distribution of System Capacity in Multiuser MIMO Systems with Large Number of Antennas

In this paper, an asymptotic distribution for the sum rate capacity is derived in zero-forcing beamforming (ZF-BF) based multiuser MIMO systems with a large number of base station (BS)antennas. By utilizing the characteristics of a large number of antennas and the central limit theorem, we prove that the asymptotic distribution for the sum rate capacity follows Gaussian distribution. Also we derive the mean and variance values for the asymptotic Gaussian distribution. Based on the asymptotic Gaussian distribution, we also obtain the outage probability for the sum rate capacity as a closed form. Simulation results show that the asymptotic Gaussian distribution is well follows the actual sum rate capacity, and the both asymptotic mean and variance value are also very accurate.

Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory

Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multilevel cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes consist of three procedures, estimation of cell-to-cell interference, compensation for cell-to-cell interference, and generation of log-likelihood ratio (LLR). First, reduced symbol pattern of interfering cells is used to estimate cell-to-cell interference by modifying the levels of the threshold voltage shift from multi page programming to two levels. Second, based on this estimation, cell-to-cell interference is compensated by modifying the read voltage considering the estimated cell-to-cell interference in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check (LDPC) codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, cell-to-cell interference can be relaxed with a simple structure and a high reliability. The bit error rate (BER) performances of the proposed schemes are compared with the conventional schemes on 8-level MLC NAND flash memory. Simulation results show that the proposed schemes show the improved BER performances by more than an order of magnitude compared with the conventional LDPC scheme.

Pilot Power Ratio for Uplink Sum-Rate Maximization in Zero-Forcing Based MU-MIMO Systems with Large Number of Antennas

This paper analyzes the pilot power ratio (PPR) in multiuser multiple-input multiple-output (MU-MIMO) systems with a large number of receive antennas (M) at the base station (BS). We consider zero-forcing based MU-MIMO orthogonal frequency division multiplexing (OFDM) systems. Based on the deterministic uplink sum-rate approximation for imperfect channel state information, we can formulate the optimization problems in terms of the PPR to maximize the ergodic uplink sum-rate subject to the per-slot or per-symbol power constraint. Under the per-slot power constraint, the optimal PPR can be obtained in a closed form while under the per-symbol power constraint, we propose an iterative algorithm which generates a suboptimal PPR. Simulation results show that the proposed PPRs perform close to the optimal performance in terms of the sum-rate. Also, it is shown that the proposed PPRs outperform the equal power allocation. In particular, in the ZF-R based MU-MIMO OFDM system with 8 users and M=32 under the per-slot power constraint, the proposed PPR can achieve about 8bps/Hz performance gain compared to the equal power allocation.

Two-Dimensional Equalization Using Bilinear Recursive Polynomial Model for Holographic Data Storage Systems

In this paper, we propose new two-dimensional (2D) nonlinear equalizers developed on the basis of a bilinear recursive polynomial (BRP) model for holographic data storage (HDS) systems. The 2D BRP equalizer (BRPE) and the 2D BRP decision feedback equalizer (BRPDFE) are proposed. The bit error rate (BER) performances of the proposed schemes are studied in the electrical-noise-dominant channel (ENDC) and the optical-noise-dominant channel (ONDC). The proposed schemes are compared with the conventional adaptive DFE and the partial response maximum likelihood (PRML) detector. The simulation results show that the proposed schemes outperform the adaptive DFE and the PRML detector. In particular, the BRPDFE shows the best BER performance in both the ENDC and the ONDC.

Two-Dimensional Iterative Decoding Schemes for Holographic Data Storage Systems

Two iterative decoding (ID) schemes, which are the ID using a single parity bit (ID-SPB) and ID using a modulation code (ID-MC), are proposed for holographic data storage systems. In the ID-SPB, a single two-dimensional parity bit is employed to conduct ID, whereas in the ID-MC, the inherent constraint of the modulation code is utilized to conduct ID. In both schemes, a data page is iteratively decoded by exchanging extrinsic information between the horizontal and vertical data bits in the page. In particular, in the ID-SPB, by adding more parity bits to each row and column of the interleaved page, we can conduct the ID within a page as well as between the original and interleaved pages. Thus, additional performance gain can be achieved in the ID-SPB. On the other hand, the ID-MC has a performance gain without loss of data rate since parity bits are not required for ID. The simulation results show that the proposed ID-SPB and ID-MC have about 2–4 and 1–2 dB performance gains in terms of bit error rate compared with the system without ID, respectively.

Iterative Decoding Method Using Two-Dimensional Single Parity Code for Holographic Data

Holographic data storage (HDS) is a promising technology because of its potential for high data storage density and high data rate [1]. In HDS systems, since the two-dimensional (2D) page signal processing is performed, we are confronted with the 2D inter-symbol interference (ISI) problem. To mitigate 2D ISI, many kinds of 2D equalizers, error correcting codes and modulation codes have been developed [2][3]. In this paper, we propose a simple but strong iterative decoding scheme ensuring high data rate based on 2D characteristics for HDS systems. By adding a single parity bit at the end of the page, we can conduct iterative decoding using the log-likelihood ratio (LLR) of the data bit. Also, the proposed iterative scheme gives the error correction capability to constant weight block code [4] without additional parity bits.