Taeik Kim

A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

A fully reconfigurable SDR contains an RX, a TX, and 2 synthesizers for true multi-standard operation. A MEMS-enabled dual-band LNA proves the feasibility of switched antenna filtering for interference robustness. The baseband section is programmable in noise level and in bandwidth from 350kHz to 23MHz. The receiver has 6dB NF, -9dBm IIP3, and up to 90dB gain. Implemented in a 0.13μmum CMOS process, it draws 62mA to 120mA in RX mode and 56mA to 89mA in TX mode from a 1.2V supply.

Microencapsulation of rosmarinic acid using polycaprolactone and various surfactants

Rosmarinic acid (RA) has a number of interesting biological activities, e.g. anti‐viral, anti‐bacterial, anti‐inflammatory and antioxidant. The antioxidant activity of RA is stronger than that of vitamin E. Despite its strong antioxidant activity, it was limited to use in cosmetics because of the low water solubility, discolouration and chemical instability. The purpose of this study was to prepare RA‐loaded polycaprolactone (PCL) microspheres using emulsion solvent evaporation method and characterize them with different surfactants used in the formation process. Finally, long‐term stability of RA was evaluated in the cosmetic formulation. As a result, PCL microspheres were found to be spherical in shape, with zwitterionic surfactant‐PCL particles being the smallest size distribution and highest entrapment efficiency of RA. Emulsions containing RA‐loaded PCL microspheres showed a better long‐term stability of the RA compared with those containing only RA. These results suggest that RA may be stably and efficiently encapsulated into polycaprolactone microspheres.

DVB-H Antenna Design Using Folder-Type Chassis and Coupling Element on a Ferrite

This letter presents a new design concept of the digital video broadcast-handheld (DVB-H) antenna using the folder-type chassis and coupling element on a ferrite. By utilizing the chassis as a radiator in conjunction with a compact coupling element on a ferrite, the antenna achieves DVB-H operation without an additional matching circuit. The measured result shows the wide bandwidth of 250 MHz (VSWR< 6) with sufficient peak gains over -5 dBi in the DVB-H band.

A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology

The first synchronous cyclic TDC is proposed in 28nm CMOS process. A novel 2x time amplifier whose gain is insensitive to variations and noise is proposed by using time conservative nature of the proposed synchronous time adder. The implemented 12b TDC occupies 0.01 mm2, consumes 820μW and it achieves 0.63ps of resolution over 2.6ns of input range.

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS

A multiplying delay-locked loop (MDLL) is an attractive architecture for a low-jitter clock generator, as it does not suffer much from jitter accumulation [1-4]. By periodically replacing the output edge of the oscillator by a clean edge of the reference, an MDLL has a large effective loop bandwidth for oscillator phase noise, which cannot be obtained in a PLL. With this advantage in mind, several MDLLs have been implemented recently [2], [3]. Unfortunately, these works are limited in their practical use as the frequency multiplication factor is only 4 [2] or 8 [3]. While the prior works show good jitter performance, it is primarily due to their wide effective loop bandwidth of nearly one hundred MHz that arises from using reference frequencies of 375 to 575MHz. It is much more challenging to achieve same level of jitter performance if the multiplication factor is increased and reference frequency is decreased. In this work, a low-power digital MDLL (DMDLL) with a multiplication factor of 32 is presented. To achieve low-jitter despite the large multiplication factor, a background-calibrated double-injection scheme is proposed which exploits both the rising and falling edge of the reference.

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology

A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs are a good example. Their performance, however, is limited by delay variation and random mismatch among delay cells, unless additional error correction or external control are applied. A time-domain successive-approximation scheme could be an option to achieve high resolution but it consumes too much power and area to generate precisely tuned delay cells. In another case, time-amplifier-based multi-step TDCs that can alleviate the requirement on the minimum unit delay of the quantization by time-difference amplification, may be an attractive option. However these tend to be power-hungry or to require additional calibration circuitries due to the inaccuracy and PVT vulnerability of the time amplifier or time register. In this paper, we present a simple, low-power, and PVT-variation-tolerant TDC architecture without any calibration, using stochastic phase interpolation and 16× spatial redundancy.

A 0.004mm 2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm 2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications

As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been sever- al approaches to convert analog systems to their digital counterparts and a high- resolution time-to-digital converter (TDC) is a key element for the digitalization of analog circuits. Recently TDCs using a noise shaping technique with oversampling have been introduced to improve resolution. However, they tend to be power hungry or require analog-intensive circuitry as they convert signals from the time domain to the voltage domain in order to perform arithmetic operations. A digital PLL (DPLL) is another crucial SoC component, and low-power area-efficient DPLLs are challenging to design. This paper presents a time-domain low-power ΔΣ TDC with a time-difference accumulator and an area-efficient, low-power, and fast-lock DPLL composed of a synthesizable bang-bang phase and frequency detector (BB-PFD), with a gain boosting mode and a pseudo-random number generator (PRNG).

A 0.026mm 2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter

Recent innovations in semiconductor processes have accelerated the transition from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from poor noise performance and high power consumption [2]. On the other hand, hybrid approaches, which employ analog components such as digital-to-analog converters (DACs), digital-to-time converters, phase interpolators (PIs) and regulators, have the typical difficulties associated with analog circuits, such as low output resistance, small voltage headroom and large variation. In this paper, we propose a highly digital architecture for a DPLL - one which minimizes the design effort typically required for analog circuits. The power and area-consuming circuits in prior works are replaced by power and area-efficient circuits with competitive performance. For example, a conventional time-to-digital converter (TDC) usually occupies considerable chip area in order to maximize input dynamic range with precise resolution [1]. Instead, in this work, a time-windowed phase-to-digital converter using interpolated DCO phases as a phase reference is adopted. In addition, conventional synchronous counters in the feedback path drastically increase the power consumption. Furthermore, retiming of data from the TDC is unavoidable due to the meta-stability of the sampling flip-flops [1]. The proposed divider scheme, which is composed of a multi-modulus frequency divider and a dead-zone-free phase and frequency detector (PFD), eliminates the need for a synchronous counter and retiming circuits. A calibration-free ΔΣ modulator (DSM) noise canceller is also included.

A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS

This brief describes a pseudodigital oscillator design for low-voltage applications. To overcome the start-up problem of the digitally controlled ring oscillator with an ultralow supply voltage, a digitally controlled relaxation oscillator (DCRXO) that utilizes an inverter-based comparator is proposed. The pseudocomparator (PC), which is a variable threshold inverter, followed by an inverter, is introduced and a digital calibration circuit is used to automatically set the threshold of the PC for process-insensitive operation in the initial state. The DCRXO implemented in 65-nm CMOS consumes 17.8 μW from a 0.35-V supply at 26-MHz output and achieves a tuning range of 18.2-29.2 MHz with a sufficient overlap between tuning curves. The phase noise of -104 dBc/Hz at 1 MHz offset is measured at 26-MHz output frequency. When the supply voltage of 0.5 V is used, the DCRXO consumes 59 μW at 100-MHz output with the tuning range of 43.5-152 MHz. The core area of the DCRXO is 0.0362 mm2.

A 0.015-mm

This brief illustrates the design of an inductorless high-speed clock generator. Compared to inductance-capacitance (