Tahir Maqsood

Dynamic task mapping for Network-on-Chip based systems

Efficiency of Network-on-Chip (NoC) based multi-processor systems largely depends on optimal placement of tasks onto processing elements (PEs). Although number of task mapping heuristics have been proposed in literature, selecting best technique for a given environment remains a challenging problem. Keeping in view the fact that comparisons in original study of each heuristic may have been conducted using different assumptions, environment, and models. In this study, we have conducted a detailed quantitative analysis of selected dynamic task mapping heuristics under same set of assumptions, similar environment, and system models. Comparisons are conducted with varying network load, number of tasks, and network size for constantly running applications. Moreover, we propose an extension to communication-aware packing based nearest neighbor (CPNN) algorithm that attempts to reduce communication overhead among the interdependent tasks. Furthermore, we have conducted formal verification and modeling of proposed technique using high level Petri nets. The experimental results indicate that proposed mapping algorithm reduces communication cost, average hop count, and end-to-end latency as compared to CPNN especially for large mesh NoCs. Moreover, proposed scheme achieves up to 6% energy savings for smaller mesh NoCs. Further, results of formal modeling indicate that proposed model is workable and operates according to specifications.

Coordinated opportunistic routing protocol for wireless mesh networks

Opportunistic routing is an emerging research area in Wireless Mesh Networks (WMNs), that exploits the broadcast nature of wireless networks to find the optimal routing solution that maximizes throughput and minimizes packet loss. Opportunistic routing protocols mainly suffer from computational overheads, as most of the protocols try to find the best next forwarding node. In this paper we address the key issue of computational overhead by designing new routing technique without using pre-selected list of potential forwarders. We propose a novel opportunistic routing technique named, Coordinated Opportunistic Routing Protocol for WMNs (CORP-M). We compare CORP-M with well-known protocols, such as AODV, OLSR, and ROMER based on throughput, delivery ratio, and average end-to-end delay. Simulation results show that CORP-M, gives average throughput increase upto 32%, and increase in delivery ratio (from 10% to 20%). We also analyze the performance of CORP-M and ROMER based on various parameters, such as duplicate transmissions and network collisions, by analysis depicts that CORP-M reduces duplicate transmissions upto 70% and network collisions upto 30%.

Scalability Issues in Online Social Networks

The last decade witnessed a tremendous increase in popularity and usage of social network services, such as Facebook, Twitter, and YouTube. Moreover, advances in Web technologies coupled with social networks has enabled users to not only access, but also generate, content in many forms. The overwhelming amount of produced content and resulting network traffic gives rise to precarious scalability issues for social networks, such as handling a large number of users, infrastructure management, internal network traffic, content dissemination, and data storage. There are few surveys conducted to explore the different dimensions of social networks, such as security, privacy, and data acquisition. Most of the surveys focus on privacy or security-related issues and do not specifically address scalability challenges faced by social networks. In this survey, we provide a comprehensive study of social networks along with their significant characteristics and categorize social network architectures into three broad categories: (a) centralized, (b) decentralized, and (c) hybrid. We also highlight various scalability issues faced by social network architectures. Finally, a qualitative comparison of presented architectures is provided, which is based on various scalability metrics, such as availability, latency, interserver communication, cost of resources, and energy consumption, just to name a few.

Energy-Aware Grid Scheduling of Independent Tasks and Highly Distributed Data

Data-aware scheduling in todays large-scale computing systems has become a major complex research issue. This problem becomes even more challenging when data is stored and accessed from many highly distributed servers and energy-efficiency is treated as a main scheduling objective. In this paper we approach the independent batch scheduling in grid environment as a bi-objective minimization problem with make span and energy consumption as the scheduling criteria. We used the Dynamic Voltage and Frequency Scaling (DVFS) model for reducing the cumulative power energy utilized by the system resources for tasks executions. We developed for data transmission a general logical network topology and policy based on the sleep link-based Adaptive Link Rate (ALR) on/off technique. Two developed energy-aware grid schedulers are based on genetic algorithms (GAs) frameworks with elitist and struggle replacement mechanisms and were empirically evaluated for four grid size scenarios in static and dynamic modes. The simulation results show that the proposed schedulers perform to a level that is sufficient to maintain the desired quality levels.

Congestion-aware core mapping for Network-on-Chip based systems using betweenness centrality

Abstract Network congestion poses significant impact on application performance and network throughput in Network-on-Chip (NoC) based systems. Efficient core mapping can significantly reduce the network contention and end-to-end latency leading to improved application performance in NoC based multicore systems. In this work, we propose a Congestion-Aware (CA) core mapping heuristic based on betweenness centrality metric. The proposed CA algorithm optimizes core mapping using betweenness centrality of links to alleviate congestion from highly loaded NoC links. We use modified betweenness centrality metric to identify highly loaded NoC links that are more prone to congestion. In contrast to traditional betweenness centrality metric, which is generally used to measure the structural/static characteristics of the system, the adapted betweenness centrality metric utilizes the volume of communication traversing through the edges (NoC links) to capture the operational and dynamic characteristics of the system. The experimental results demonstrate that our proposed algorithm achieved significantly lower average channel load and end-to-end latency compared to the baseline First Fit (FF) and Nearest Neighbor (NN) core mapping algorithms. Particularly, CA algorithm achieved up to 46% and 12% lower channel load and end-to-end latency compared to FF algorithm, respectively. Moreover, proposed algorithm exhibits an average gain of 32% in terms of reduced network energy consumption compared to the baseline configuration.

Energy and communication aware task mapping for MPSoCs

Abstract Minimizing energy consumption and network load is a major challenge for network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs). Efficient task and core mapping can greatly reduce the overall energy consumption and communication overhead among the interdependent tasks. In this paper, we propose a novel Knapsack based bin packing algorithm for workload consolidation that places tasks in such a manner that utilization of available processing elements is maximized, while network overhead, regarding the communication among the tasks, is minimized. We also propose a task swapping algorithm that attempts to further optimize the task placement produced by the bin packing algorithms. Moreover, several core mapping techniques are implemented and the performance of each technique is evaluated under varying configurations. In addition, we also apply a Pareto-efficient algorithm, on top of the bin packing algorithms, attempting to explore the solution in two dimensions, i.e., energy consumption and network load. The experimental results show that the proposed Knapsack based bin packing algorithm coupled with the Pareto-efficient algorithm achieves significant energy savings and reduction in network load as compared to state-of-the-art algorithms, as well as the greedy algorithm. Particularly, the Pareto-efficient algorithm when applied on top of the Knapsack algorithm shows on average 50% and 55% reduction in energy consumption and network load as compared to the greedy algorithm, respectively. While the proposed Pareto-efficient algorithm applied with Knapsack algorithm also demonstrate superior performance compared to three other state-of-the-art heuristics.

Adaptive Opportunistic Routing over DTMANETS: Proposals and Issues

The convenience of small, cheep, and mobile communication devices such as laptops, cell phones, handheld devices, and mobiles sensor nodes, has popularized mobile ad hoc networks (MANETs). With the convenience, interconnection among these devices introduced new dimensions of challenges for the technology to be used for communication. Such challenges include wireless communication, mobility, and portability. Furthermore, the sparse behavior of nodes in turbulent areas, where connectivity is commonly not possible all the time, resulted in yet another exciting technology known as delay tolerant networks (DTNs). This work is related to the association of opportunistic techniques with different scenarios in which different opportunistic elements of relay nodes, e.g. message storage capacity, territory and velocity are classified according to its usefulness in a given scenario.

Leveraging on Deep Memory Hierarchies to Minimize Energy Consumption and Data Access Latency on Single-Chip Cloud Computers

Recent advances in chip design and integration technologies have led to the development of Single-Chip Cloud computers which are a microcosm of cloud datacenters. Those computers are based on Network-on-Chip (NoC) architectures with deep memory hierarchies. Developing scheduling algorithms to reduce data access latency as well as energy consumption is a major challenge for such architectures. In this paper, we propose a set of algorithms to jointly address the problem of task scheduling and data allocation in a unified approach. Moreover, we present a feasible system model for NoC based multicores considering a three-level memory hierarchy that effectively captures the energy consumed by various elements of system including: processing cores, caches, and NoC subsystem. Simulation results show the superiority of proposed algorithms compared to two state-of-the-art algorithms found in the literature. The experimental results clearly indicate that algorithms performing data and task scheduling in a joint fashion are superior against techniques implementing task and data scheduling separately.