Takafumi Chida

Recent Issues in International Supply Chain Network Design—Economic Partnership Modeling

In this paper, we present a supply chain network design technique with a preferential tariff under an economic partnership agreement. The proposed model has constraints to judge whether a preferential tariff applies under two types of rules which identify the product origin country. This model can estimate the cost reduction amount under preferential tariff utilization, and design the minimum total cost supply chain network. We show results of some case studies of factory location selection under the assumption that applicable new tariff schemes will go into effect and labor cost will rise remarkably in the future. These results suggest two types of strategies: selecting the lowest location and selecting high-cost locations for which a preferential tariff applies. It is confirmed that the proposed model can effectively perform such a quantitative evaluation.

Failure rate estimation of each process layer using critical area analysis and failing bit results

We propose a novel method by which to accurately estimate the failure rate of each process layer on a wafer-by-wafer basis. In this method, we use the failing bit data and the results of critical area analysis (CAA) of each failing bit signature (FBS). We formulate the estimation as a linear programming model and convert the failure rate of each FBS to the failure rate of each process layer. A comparison of the failure rate estimated using this method and that obtained by test structure analysis reveals good agreement and the total estimation error of all process layers are within several percent. We also improved a legacy yield management system by implementing this estimation method. This system is used for failure analysis during semiconductor manufacturing. We show two case studies for 65 nm and 45 nm technology node products.

Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area Simulation

We propose an advanced approach to accurately estimate wafer-wafer variation of random defect density in each process layer (<i>D</i>0_l) using fail bit analysis and critical area simulation. The proposed method formulates <i>D</i>0_l estimation using a linear programming model with constraint set of <i>D</i>0_l is positive. The <i>D</i>0_l estimation results are consistent with the test vehicles. We also illustrate some effective application results for yield improvement activities in the semiconductor manufacturing line.