Takahide Ikeda

Future BiCMOS technology for scaled supply voltage

A BiCMOS technology for future scaled supply voltage, V/sub x/, is described. Delay time reduction by around 100 ps is achieved by introducing a proposed base electrode surround emitter transistor (BEST). Two types of gates, CBiCMOS and BiNMOS, provide shorter gate delays and higher drivabilities than the CMOS gate even with V/sub s/, of 3.3 V. It is concluded that the innovations in the bipolar transistor structure BEST and in the CBiCMOS and BiNMOS gate circuit configuration are highly promising in comparison to CMOS ULSIs for future high-speed and high-density ULSIs operating at scaled supply voltages.<<ETX>>

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSIs. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm2) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.

Advanced BiCMOS technology for high speed VLSI

This paper describes the high performance BiCMOS (Hi-BiCMOS) device technology and discusses the scalability to sub-micron. As the device structure is scaled down from 2 µm to 1.3 µm, BiCMOS circuit performance is improved by the factor of the scaling. By further scale down to 0.8 µm, a 0.27 ns gate delay in BiCMOS gate and 5.5 ns access time of 64kbit BiCNOS ECL RAN are expected.

High speed BiCMOS VLSI technology with buried twin well structure

Bipolar transistors of high cut off frequency (f_{T}=9GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.

A 13ns/500mW 64Kb ECL RAM

This paper will cover the design of a 16K×4 SRAM which uses buried twin-well 2μm CMOS transistors and 4GHz cutoff frequency bipolar transistors. The circuit combines a high-resistance polysilicon - load NMOS memory cell with mixed MOS/bipolar periphery circuits to achieve ECL compatibility, 13ns access times and an operating power of 500mW at 40MHz.

Performance and structures of scaled-down bipolar devices merged with CMOSFETs

Fabricating BiCMOS test samples, performance and structures of 2 µm and scaled BiCMOS are evaluated. The developed BiCMOS processes realize almost the same device characteristics of bipolar and CMOS LSIs fabricated with the same lithographic technology. The intrinsic delays of BiCMOS and CMOS 2-NAND circuits are 0.5 ns and 0.4 ns respectively. The delay times are comparable with the bipolar ECL circuits. The BiCMOS technology makes it possible to fabricate high-speed, low-power dissipation, high-packing density LSIs by sharing the roles among them.

A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

A 0.2-/spl mu/m bipolar-CMOS process technology on a bonded SOI wafer was developed for ultra-high-speed applications. This process was used to fabricate a new cache memory chip consisting of 9-Mb 0.6-ns SRAMs and a 200-K 25-ps ECL gate array. To achieve high performance, the 0.2-/spl mu/m bipolar-CMOS process features a 6-/spl mu/m/sup 2/-cell-size BJT with a 50-nm base width, a 6T-CMOS memory cell and copper interconnects that reduce wiring delay by 30%. A combination of low-energy ion-implantation and two-step annealing was applied to form a low-leakage, shallow base junction. A bonded SOI wafer with deep and shallow trench isolations was used to maximize the BJT performance.

A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

An ECL (emitter-coupled-logic) 512-kb BiCMOS SRAM (statistic random access memory) with 1-kG logic and using 0.8- mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is described. The RAM has 5-ns address access time and 2-ns write-pulse width. The logic gate has 150-ps propagation delay with 4-mW power dissipation. A RAM-with-logic configuration is adopted to eliminate interconnection delay between the RAM and peripheral logic and to facilitate a wide-bit RAM. The design rule dependence of the delay time of a three-input ECL OR/NOR gate and a two-input BiCMOS NAND gate is shown. On-chip address access times, under 5 ns from address latches to data-out latches at room temperature with a marching test pattern, are also shown. Major characteristics of the LSI are presented.<<ETX>>

A 7ns/350mW 64K ECL compatible RAM

A 64K×1 ECL RAM using 1.3μm bipolar-CMOS technology including bipolar transistor with a 7GHz cutoff frequency will be presented. Variable impedance and equalizing circuitry permit 7ns access time. Power dissipation is 350mW.

A 6ns 4Kb bipolar RAM using switched load resistor memory cell

current memory cell operation and fast word line switching are the keys to fast, large capacity (above 4Kb) bipolar RAMs. However, it is difficult to achieve this performance in large capacity memories with conventional parallel diode memory cells’. This problem was overcome with a switched load resistor memory cell; Figure 1. At standby, the load resistance of the memory cell is high ( R ~ ~ 1 5 0 k f i ) . When the memory cell is selected, a read current flows through Schottky diodes, and consequently, the load resistance is automatically switched to a lower value ( R ~ = 2 5 0 f i ) . This load resistor switching affords a large read current (2mA), smaller standby current (4pA) and a fast memory cell readtime of 0.511s. Power dissipation does not increase in spite of the large read current, because the read current is directed only to the selected memory cell by the use of a switched read current It has been found by computer simulation that large-read-