Takahiko Ishizu

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating

A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and recovery time of 10 clock cycles (including data restoration time (100 ns)). Further, memory cell area and performance in combining a 45-nm Si SRAM memory cell with 60-nm CAAC-OS are estimated to have negligible overhead.

16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using V t , cancel write method

As the number of devices connected to the Internet increases, servers and mobile devices must process increasingly large volumes of data, and also accommodate the increasing demand for high-speed and large-capacity working memory keeping the power consumption low. This need is being fulfilled by emerging devices, such as resistive RAM, phase-change RAM, and MRAM [1], which realize high-speed, high-density and nonvolatile memory, significantly enhancing the performance of CPUs with integrated memories.

State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor

As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard to achieve low power consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits to make power gating more efficient with less static power. In this paper, we propose two novel state-retention flip-flop designs based on a parallel and series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can achieve state retention with zero static power. To demonstrate the application of these different designs, they are implemented in a 32-bit normally-off microprocessor with an energy break-even time of 1.47 µs for the parallel type design and 0.93 µs for the series type design, at a clock frequency of 15 MHz. We show that decreasing the power supply duty cycle to 0.9%, the average current of the processor core can be decreased by over 99% using either type of flip-flop.

Temperature-Induced Valence Transition of EuPd2Si2 Studied by Hard X-ray Photoelectron Spectroscopy

We have studied the electronic structure of EuPd2Si2 by hard X-ray photoelectron spectroscopy (HX-PES) from 300 to 20 K. The temperature-dependent HX-PES spectra clearly show the valence transition, namely, the intensities of the divalent and trivalent Eu 3d components are abruptly changed. The change in Eu 3d spectral shape, especially the drastic change in the trivalent Eu 3d feature with temperature, can be explained within the framework of the Anderson model. The peak shift of Pd 3d core level with temperature indicates that the valence electrons of Pd contribute to the temperature-induced valence transition of EuPd2Si2.

A 16-Level-Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET

A 16-level cell is demonstrated using a test chip of nonvolatile oxide semiconductor RAM comprising c-axis aligned crystalline In-Ga-Zn oxide FETs. A read circuit composed of voltage followers outputs a read voltage with a maximum distribution of 37 mV. A single voltage follower has a maximum distribution of the read voltage of 25.3 mV. A 200 ns write time of the test chip is demonstrated.

A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology

An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than 1 zA (10−21 A) was fabricated. In the 2T1C gain cell, an OSFET for the write operation was stacked over a SiFET for the read operation. The 1 Mbit macro was fabricated using a combination of 60-nm OSFET and 65-nm CMOS processes. It achieves a 140 MHz operation and data retention of more than 1 h. Its static power in the standby state and active power are 31 μW and 64 μW/MHz, respectively. The macro with long-term data retention can reduce the static power by power gating. 2T1C OSFET-based embedded memory is applicable to devices requiring high performance as well as low power.

A 16-level-cell memory with c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide FET using threshold voltage cancel write method

We demonstrate a 16-level cell using a nonvolatile oxide semiconductor random access memory test chip based on c-axis-aligned a–b-plane-anchored crystal In–Ga–Zn oxide (CAAC-IGZO) FETs. The memory cell consists of a CAAC-IGZO FET, a p-channel metal–oxide–semiconductor Si FET, and a cell capacitor. Data are written using a threshold voltage cancel write method, and a read circuit composed of voltage followers outputs a read voltage. Using a 200 ns write time of the test chip, the obtained maximum read voltage distribution width is 37 mV in the case of 32768 memory cells. The distributions of 16 read voltages are separated from each other without overlapping, with a single voltage follower exhibiting a maximum read voltage distribution width of 25.3 mV. In the −40 to 85 °C temperature range, the voltage distribution range is 0.13 V, and the variation due to varying temperatures is 0.24 mV/°C.

Embedded SRAM and Cortex-M0 Core with Backup Circuits using a 60-nm Crystalline Oxide Semiconductor for Power Gating

Using data retention circuits that include crystalline oxide semiconductor transistors as backup circuits for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications that require standby power reduction. The crystalline oxide semiconductor transistor can constitute a nonvolatile data retention circuit easily because it exhibits significantly lower off-state current than a silicon transistor and is highly compatible with a CMOS logic circuit. The backup circuit can achieve 2-clock-cycle data backup and 4-clock-cycle data restore; thus, the processor system can efficiently perform temporally fine-grained power gating and can achieve longer standby times. Furthermore, area overheads due to the backup circuits are kept very small because the crystalline oxide semiconductor transistors are stacked on silicon transistors.

Peculiar Linear Dispersive Bands Observed in Angle-Resolved Photoemission Spectra of Tl-Based Ternary Chalcogenide TlGaTe2

Electronic energy bands of the Tl-based ternary chalcogenide TlGaTe2 with a quasi one-dimensional crystalline structure have been studied by means of high resolution angle-resolved photoemission spectroscopy (ARPES) in order to check for dispersive structures similar to the Dirac cone observed in the surface bands of Bi-based binary chalcogenides. Two linear dispersive structures which are not reproduced in band calculations for bulk material have been observed in the energy band along the Γ–N direction perpendicular to the chains. These dispersions form a cross-type structure that is centered at the Γ point and extends along the Γ–H–T direction parallel to the chains, reflecting, in our opinion, one-dimensional features of surface morphology of TlGaTe2. The cross-type structure, the energy position of which linearly varies with excitation photon energy, is observed only for high-grade quality surfaces of TlGaTe2. It is therefore assumed that the observed peculiar dispersive structure is caused by the Dirac-type dispersion of high-lying surface conduction bands and that ARPES detects the joint density of states.