Takahiko Mitsui

Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal

We describe a through-silicon via (TSV) reveal process that uses direct Si/Cu grinding and metal contamination removal for the backside reveal of small-diameter (4 μm) TSVs. In this process, simultaneous grinding of Cu and Si was performed by using a novel grinding wheel (vitrified-bond type) and cleaning the grinding wheel with a high-pressure micro jet. Owing to the inelastic porous structure and in situ cleaning of the grinding wheel, the adhesion of Cu contaminants to Si was suppressed during grinding, and the TSVs could be leveled and revealed without burning and smearing of Cu. After this, electroless Ni-B plating was performed in order to prevent etching of Cu in the TSVs, and alkaline etching of Si was performed to reduce slight Cu contamination generated by direct Si/Cu grinding. As a result, TSVs were revealed uniformly and the K, Ni, and Cu contaminants in the Si region between TSVs were suppressed to below 5 × 1010 atoms/cm2.

Metal contamination evaluation of a TSV reveal process using direct Si/Cu grinding and residual metal removal

We evaluated the metal contamination generated by a through silicon via (TSV) reveal process using direct Si/Cu grinding and residual metal removal. To evaluate the metal contamination, a complementary metal oxide semiconductor (CMOS) + TSV wafer was prepared. The diameter and depth of the TSVs were 20 μm and 50 μm, respectively. TSV density was approximately 10%. The distance between each circuit component and TSV was 60 μm. After it was bonded to a glass support substrate, a TSV reveal process was performed by using direct Si/Cu grinding and residual metal removal. The wafer thickness after the TSV reveal process was 38 μm. After the TSV reveal process, the leakage current of the n+/p diodes and the capacitance-time characteristics of the n-type MOS capacitors were measured. The leakage current of the n+/p diodes was virtually unchanged after the TSV reveal process. In addition, the change in the generation lifetime of minority carriers determined by Zerbst analysis was less than 6%. These results demonstrate that the influence of the TSV reveal process on circuit components is small.

Improvement of a TSV Reveal Process Comprising Direct Si/Cu Grinding and Residual Metal Removal

We improved a through-silicon via (TSV) reveal process comprising direct Si/Cu grinding (simultaneous grinding of Si and Cu) and residual metal removal. In this improved process, direct Si/Cu grinding was performed by using a novel grinding wheel (vitrified-bond type) and cleaning the wheel with a high-pressure micro jet. Instead of electroless Ni-B plating, electroless Sn plating was then performed to cover the Cu surface in the TSVs. Finally, alkaline etching of Si was performed to reduce the slight Cu contamination generated by the direct Si/Cu grinding. The Sn film acted not only as a protective layer but also as a direct bonding material for 3D chip stacking. Time-of-flight secondary ion mass spectrometry analysis showed the Cu contaminant concentration at the Si region to be below 5×1010 atoms/cm2 even when the electroless plated Sn film was used. We also performed 3D stacking of a 35-μm-thick Si chip using TSVs revealed by this improved process. As a result, a very thin chip could be simply stacked without any damage. These results demonstrate that this process enables simple 3D integration without Cu contamination.

Investigation of metal contamination induced by a through silicon via reveal process using direct Si/Cu grinding and residual metal removal

We investigated metal contamination induced by a through silicon via (TSV) reveal process using direct Si/Cu grinding and residual metal removal. A complementary metal oxide semiconductor (CMOS) wafer including TSVs was bonded to a glass support substrate, and a TSV reveal process was performed by direct Si/Cu grinding and residual metal removal. Then, metal contamination near the SiO2/Si interface on the front side of the wafer was investigated by using a pulsed-MOS capacitor technique and measuring the effective generation lifetime and effective surface generation velocity before and after this TSV reveal process. The results of Zerbst analysis showed that the changes in average effective generation lifetime and average effective surface generation velocity were −5.4 and +4.2%, respectively. These results demonstrate that the effect of metal contamination induced by our TSV reveal process on circuit components is small.

Wafer Handling and Thinning Processes

Wafer thinning/handling is one of the most important technology to enable TSV. More than ten years, many researchers and engineers have made great efforts to establish the process.