Takahiro Ando

Translation rules of SysML state machine diagrams into CSP# toward formal model checking

Purpose – This study aims to describe the behavior of blocks in the system under consideration using systems modeling language (SysML) state machine diagrams. In this paper, formalization and model checking for SysML state machine diagrams have been investigated. Design/methodology/approach – The work by Zhang and Liu (2010) proposed a formalization of SysML state machine diagrams in which the diagrams were translated into CSP# processes that could be verified by the state-of-the-art model checker PAT. In this paper, several modifications have been made and new rules have been added to the translation described in that work. Findings – First, three translation rules were modified, which apparently are inappropriately defined according to the SysML definition of state machine diagrams. Next, we add new translation rules for two components of the diagrams – junction and choice pseudostates – which have not been dealt with previously. Further, we are implementing the automatic translation system on a web-bas...

Towards Formal Description of Standards for Automotive Operating Systems

The OSEK/VDX specification is a standard for automotive operating systems, i.e., operating systems for mobile vehicles. The specification is described in a natural language. Thus, it is difficult to verify the conformity that the automotive operating systems follow this standard due to its ambiguity. We think that such standard has to be formally described enough to ensure that final products conform to the standard. In this paper, we propose a framework for formalization of the OSEK/VDX specification.

Operation Phase Metrics for Smart Mobility Platform

This paper identi es metrics that can be used in the operation phase to realize a platform to facilitate the development of services for smart mobility. The paper analyzes requirements of the platform for smart mobility using the I* framework which facilitates identi cation of goals between stakeholders. We conduct goal-question-metric(GQM) identifying metrics, which can evaluate whether the application or platform meets the goals that we have identi ed through the I* analysis.

Garakabu2: An SMT-based Bounded Model Checker for HSTM Designs in ZIPC

Hierarchical State Transition Matrix (HSTM) is a table-based modeling language that has been broadly used for developing software designs of embedded systems. In this paper, we describe a model checker Garakabu2, which we have been implementing for verifying HSTM designs against LTL properties. The HSTM designs that Garakabu2 takes as input are those developed using an industrial-strength model-based development tool ZIPC. We focus on describing Garakabu2s verification techniques and performance as well as our effort to improve its practical usability for on-site software engineers. Some experience and lessons on developing industry-oriented model checkers are also reported.

A Survey of Acceleration Techniques for SMT-Based Bounded Model Checking

Model checking is wildly acknowledged to be an effective formal technique for verifying that a finite state system satisfies desired properties expressed in temporal logic. There are primarily two types of model checking approaches: explicit model checking and symbolic model checking. To mitigate the notorious state exploration problems suffered by explicit model checking, bounded model checking (BMC) has been proposed as an alternative to other symbolic model checking approaches based on binary decision diagrams. Although originally SAT solvers are used by BMC as the reasoning engine, a recent trend is to switch from SAT to SMT solvers. In this paper, we survey contributions on acceleration of SMT-based BMC. In addition, we discuss some related techniques that could be potentially used as well for the acceleration purpose.

Harnessing SMT-Based Bounded Model Checking through Stateless Explicit-State Exploration

We propose a hybrid approach to improving the verification performance of SMT-based bounded model checking for LTL properties. In this approach, stateless explicit-state exploration is utilized to traverse, under the constraints of bounded context switches, the state space of a system design and memorize legal execution paths. These paths are classified according to certain predicates into path clusters, which are then encoded into propositional formulas representing, together with the encoded formula for an LTL property, independent BMC instances. Such BMC instances are solved with SMT solvers running on mutilcores in parallel. Once a counterexample is found for one of the instances, the entire model checking terminates. This hybrid checking procedure progresses in an incremental fashion until either a counterexample is found or the user-specified bound is reached. We have implemented this proposed hybrid approach in a tool called Garakabu2 with CVC4 as its backend solver. The experimental results show that Garakabu2 often outperforms the state-of-the-art pure BMC methods implemented in SAL infinite bounded model checker for both safety and liveness properties.

Toward Sustainable Smart Mobility Information Infrastructure Platform: Project Overview

Smart mobility systems, which include Intelligent Transportation Systems (ITS) and smart energy ones, become more important. There is, however, lack of its platform studies. This paper proposes a sustainable information infrastructure project for smart mobility systems. The project pursues issues that establish an information infrastructure architecture and a seamless development method chain for it. The project has mainly two features: (1) applying life-cycle-oriented methods, which are a cycle from system development phase to operation phase. In addition, these methods are applied to real world applications, and (2) dealing with an uncertainty that occurs in system development upper phase. This paper describes an overview of the project.

ZipPath: A Simple-But-Useful Path Finder for HSTM Designs in ZIPC

Assuring functional correctness of smart mobility platforms is a critical task for enhancing reliability and safety. Hierarchical State Transition Matrix (HSTM) is a popular software design language, which can also be used for designing fundamental software of smart mobility platforms. For HSTM designs with complex hierarchical structure, it is often helpful if paths, which lead from the first-time value-change of a variable to subsequent references of the variable, can be easily understood by HSTM designers. In this paper, we describe an automatic tool called ZipPath, which can output such paths, including the shortest one, of an HSTM design. We examine the effectiveness of ZipPath with a running example. Although simple, ZipPath can be practically helpful for designers to develop correct HSTM designs.

Reference Model of specifications toward Independent Verification and Validation

Independent Verification and Validation (IV&V) [1] has begun to be used in the verification phase of system development. In this paper, we present the document group which we call “Reference Model” that we are developing currently. The Reference Model is developed for the purpose of supporting the efficient implementation of the formal verification for requirements and design specifications in IV&V. The Reference Model shows what with formats the requirement and design specifications should be described. For developers side of IV&V, the Reference Model are useful to recognize the essential information and its notation that should be described in the document that is a target of formal verification. For verifiers side, by comparing the Reference Model and the target document of the formal verification, the Reference Models are useful to recognize which items and properties should be verified.