Takakazu Kurokawa

3-D VLSI technology in Japan and an example: a syndrome decoder for double error correction

Abstract This paper consists of two parts. The first part is a survey of Three-Dimensional (3-D) VLSI technology which is considered to be one of the leading areas among the integrated circuit technologies in the next century. Furthermore the researches of 3-D VLSI in Japan are summarized as well. In the second part of this paper, as a case study, the features of 3-D VLSI are exhibited by testing various layouts of syndrome decoder for double-error correction of linear codes, which can be used for example to improve the reliability of main memories. By the layout results of DEC-BCH decoder, material as well as time savings using 3-D VLSI technology compared to the conventional 2-D VLSI technology are shown.

Neural network parallel computing for BIBD problems

Neural network parallel computing for balanced incomplete block design (BIBD) problems is presented. A design in which all the blocks contain the same number of varieties, and all the varieties occur in the same number of blocks, is called a block design. A block is said to be incomplete if it does not contain all the varieties. If a design is balanced, it is called a balanced incomplete block design. Two methods for BIBD problems have been proposed. One uses the notion of the finite fields, and the other uses the notion of the difference sets. In general, the conventional algorithms are only able to solve the problems that satisfy an affine plane or a finite projective plane. The proposed algorithm is able to solve BIBD problems regardless of the condition of an affine plane or a finite projective plane. The proposed algorithm was verified by simulation runs. The simulation results demonstrated that the number of iteration steps for the system to converge to the solution increases slightly with the problem size. >

Fast matrix solver in GF(2)

In this paper a parallel and piplined fast matrix equation solver in GF(2) is proposed where the elements are 0s or 1s. The solver employing the iterative logic circuits which are suitable for VLSI implementation can be realized by the conventional Gauss Jordan Elimination Method. O(n) gate stages in the pipeline and O(n3) total gates are required for solving A X = b where A is a matrix of n×n, X and b are vectors respectively. The organization of the solver is discussed in this paper.

A neural network approach to broadcasting in multihop packet radio networks

A neural network model for broadcasting scheduling in multihop packet radio networks is presented. The problem of broadcast scheduling with a minimum number of time slots is NP-complete. The proposed neural network model finds a broadcasting schedule with a minimal number of time slots, and requires n processing elements for an n-node radio network. Fifteen different radio networks were examined where the neural network model found an m-time-slot solution in O(m) time with n processors.<<ETX>>