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Dive into the research topics where Takaki Yoshida is active.

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Featured researches published by Takaki Yoshida.


asian test symposium | 2002

MD-SCAN method for low power scan testing

Takaki Yoshida; Masafumi Watari

As semiconductor manufacturing technology advances, power dissipation and noise in scan testing have become critical problems. Our studies on practical LSI manufacturing show that power supply voltage drop causes testing problems during shift operations in scan testing. In this paper, we present a new testing method named MD-SCAN (multi duty-scan) which solves power supply voltage drop problems, as well as its experimental results applied to practical LSI chips.


asian test symposium | 1999

Practical application of automated fault diagnosis for stuck-at, bridging, and measurement condition dependent faults in fully scanned sequential circuits

Reisuke Shimoda; Takaki Yoshida; Masafumi Watari; Yasuhiro Toyota; Kiyokazu Nishi; Akira Motohara

A practical fault diagnosis system based on combination automatic test pattern generation (ATPG) and fault simulation is described. Our fault diagnosis system deals with conventional stuck-at and bridging faults, as well as measurement condition dependent (MCD) faults in order to diagnose those faults causing different behavior with measurement condition such as supply voltage and temperature, using single stuck-at based diagnosis techniques. Experimental results with a practical very deep submicron (VDSM) LSI circuit shows that a defective chip can be efficiently diagnosed using our diagnostic algorithm and newly proposed MCD fault model.


asian test symposium | 1997

An effective fault simulation method for core based LSI

Takaki Yoshida; Reisuke Shimoda; Takashi Mizokawa; Katsuhiro Hirayama

We examined effective usage of fault simulation to reduce enormous handling time for fault simulation, and applied it in our LSI development. Random sampling method, DFS (Distributed Fault Simulation), a selection of most suitable FPP(faults per pass) and elimination of hyper faults are applied here to realize necessary handling speed of dozens of times faster than the present usage. It is effective in a fault simulation to simulate the best vector first that increases the fault coverage most. Furthermore, we would like to give a new suggestion that the density of mask patterns is taken into consideration as a factor of fault coverage and also its physical correctness is estimated.


Archive | 2006

Fault detecting method and layout method for semiconductor integrated circuit

Takaki Yoshida; Reisuke Shimoda


Archive | 2004

Semiconductor integrated circuit verification method and test pattern preparation method

Takaki Yoshida; Keisuke Ochi


Archive | 2004

Error portion detecting method and layout method for semiconductor integrated circuit

Takaki Yoshida


Archive | 2007

Methods for designing and testing semiconductor integrated circuits with plural clock groups

Takaki Yoshida


Archive | 2003

Method for designing semiconductor integrated circuit and method for testing the same

Takaki Yoshida


Archive | 2007

Semiconductor integrated circuit verifying and inspecting method

Takaki Yoshida


IEICE Transactions on Information and Systems | 2004

A New Solution to Power Supply Voltage Drop Problems in Scan Testing

Takaki Yoshida; Masafumi Watari

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