Takao Marukame

Electrical Spin Injection into n-GaAs Channels and Detection through MgO/CoFeB Electrodes

Spin injection and detection between MgO tunnel barrier/CoFeB electrodes and n-GaAs channels were investigated by means of all electrical transport measurements. The magnetoresistance of the GaAs/MgO/CoFeB junctions and non-local signals through the lateral GaAs channel were detected in the same sample. The non-local signals were detected when the magnetization directions of two CoFeB electrodes differed. This correspondence between the magnetization directions and the non-local signals clearly shows that the injection and detection of the spin-polarized current are realized in the GaAs/MgO/CoFeB systems.

Extracting Physically Unclonable Function From Spin Transfer Switching Characteristics in Magnetic Tunnel Junctions

Hardware security devices that include physically unclonable function (PUF) hold significant advantages over software-based secure identification and key storage. We propose a PUF for magnetic tunnel junctions (MTJs) and a method for extracting PUF based on intrinsic properties of spin transfer switching (STS). The STS characteristics of MTJs with perpendicular layers were measured and analyzed to determine how to extract PUF properties. Given the experimental intrinsic stochastic properties combined with the proposed sequence, we discuss the PUF properties extracted from MTJs. To realize secure hardware key in non-volatile devices, our methods and results are promising for constructing MTJ-PUF based on spintronic LSI devices.

Impact of platinum incorporation on thermal stability and interface resistance in NiSi/Si junctions based on first-principles calculation

We studied extremely low interface resistance and thermal stability of the interface of NiSi/Si junctions with Pt (Ni(Pt)Si/Si junctions) based on first-principles calculation. The physical origin of thermal stability of NiSi enhanced by Pt is clarified by the calculations. Our calculations show clear difference of energies for dopant atoms of As and B between PtSi/Si and NiSi/Si. The results obtained theoretically and experimentally in this study demonstrate the dipole comforting Schottky junctions enhanced by PtSi at the interface for extremely low resistance.

Read/write operation of spin-based MOSFET using highly spin-polarized ferromagnet/MgO tunnel barrier for reconfigurable logic devices

For future high-performance reconfigurable logic devices, we developed a novel spin-based MOSFET; “Spin-Transfer-Torque-Switching MOSFET (STS-MOSFET)” that enables the read/write performance and memorization of the configuration with nonvolatility by using the ferromagnetic electrodes and the spin-polarized current through Si channel and spin-transfer torque switching in magnetic tunnel junctions (MTJs) on the source/drain. The read/write operation of the STS-MOSFET was first demonstrated in this work. The highly spin-polarized ferromagnet/MgO tunnel barrier electrodes and the MTJs using their structure for the source/drain showed great possibility to realize our proposed STS-MOSFET and to enhance their performance.

Scalability of spin field programmable gate array: A reconfigurable architecture based on spin metal-oxide-semiconductor field effect transistor

The scalability of a field programmable gate array (FPGA) using a spin metal-oxide-semiconductor field effect transistor (MOSFET) (spin FPGA) with a magnetocurrent (MC) ratio in the range of 100–1000% is discussed for the first time. The area and speed of million-gate spin FPGAs are numerically benchmarked with CMOS FPGA for 22, 32, and 45 nm technologies including a 20% transistor size variation. We show that the area is reduced and the speed is increased in spin FPGA due to the nonvolatile memory function of spin MOSFET.Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin FPGA owing to the nonvolatile memory function of spin MOSFET.

Reconfigurable characteristics of spintronics-based MOSFETs for nonvolatile integrated circuits

Reconfigurability of a novel spintronics-based MOSFET; “Spin-transfer-Torque-Switching MOSFET (STS-MOSFET)” was successfully realized in the transport properties. The device showed magnetocurrent (MC) and write characteristics with the endurance of over 105 cycles. It was clarified that the read and write characteristics (i.e., MC ratio and write voltage) can be improved by choosing connection configurations of the source and the drain in the STS-MOSFETs. Large scale circuit simulations for various circuits in FPGA revealed that the critical path delay is significantly improved by using the STS-MOSFETs. The overall properties of the STS-MOSFETs show great potentialities for future reconfigurable integrated circuits based on CMOS technology.

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology

A silicon physically unclonable function (PUF) using ring oscillators (ROs) has the advantage of easy application in both an application specific integrated circuit (ASIC) and a field-programmable gate array (FPGA). Here, we provide a RO-PUF using the initial waveform of the ROs based on 65 nm CMOS technology. Compared with the conventional RO-PUF, the number of ROs is greatly reduced and the time needed to generate an ID is within a couple of system clocks.

Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA

Real-time results obtained from an unsupervised feature extraction system using Restricted Boltzmann Machines (RBMs) implemented on FPGA are presented. The feature extraction application is demonstrated using the MNIST dataset, and the weights storing features are visualized in real-time. A digit classification is also performed based on the learning results. Our demonstration system performs 134 times faster than the compared conventional CPU.