Takao Nishida

A structure and technique for pseudorandom-based testing of sequential circuits

Presented is a register structure and generator design which enables non-scan sequential testing using parallel pseudorandom-based patterns applied to the circuits primary inputs. The proposed register structure and register control strategy uses the circuit under tests (CUTs) natural sequential activity to periodically alter a registers output bias to a value near 0.5 (i.e. alter the spread of 1s in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom-based test patterns are applied to the input lines of a CUT. Using the register modification, a simple hardware generation system can be designed and is suitable for both on-chip and external testing. Experiments indicate that high fault coverage is attainable in a relatively short test time.

RFSIM: Reduced Fault Simulator

This paper describes the algorithm, implementation, and evaluation results of a new fault simulator called RFSIM, which is designed for combinational circuits. In order to accelerate fault simulation, two basic principles are introduced, a Detectable Fault Only (DFO) principle and a Candidate Gate Once (CGO) principle. The DFO principle is a dynamic reduction algorithm, which aims at drastically reducing computational complexity by utilizing blocking gate information. The CGO principle is an implementation technique which is utilized to implement the DFO principle effectively. Experimental results show that RFSIM is more than 10 times faster than a conventional concurrent fault simulator, and confirms that the DFO principle contributes to a drastic reduction in the number of faults to be simulated. A fault reduction ratio of around 25 to 1 was achieved in one of the benchmark circuits.

VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults

A new fault simulator (VFSIM) for synchronous sequential circuits has been developed and applied to random access scan circuits of several hundred LSIs in mainframe computers. The results show that VFSIM is one or two orders of magnitude faster than a conventional fault simulator designed for random access scan circuits. A vectorized pattern parallel event-driven method is introduced for accelerating the fault simulator for synchronous sequential circuits. Utilizing the concept of unobservable regions (UOR), in which simulation of temporarily unobservable faults is avoided, contributes greatly to further acceleration, especially for random access scan circuits.