Takashi Sakao

Design considerations of the Matsushita 32-bit microprocessor for real-memory systems

A high-speed, high-performance 32-bit microprocessor for real-memory systems is described that is now being developed based upon TRONCHIP specifications. The principle applications of this processor are as a high-performance controller for control devices, communications, networks, graphics, etc.; as a high-performance specific LSI core; and as a CPU for personal computers, word processors, etc. It has been designed to achieve a performance of 8 MIPS (million instructions per second) at a 20 MHz clock rate within the chip size which makes future ASIC development possible. As a result, design is now progressing toward one-clock execution of register-to-register instructions, speeded up load and store instructions, reduced number of pipeline stages (4 stages and a store buffer), and incorporation of the instruction cache.

An examination of the fundamental configuration of the microprocessor for virtual memory systems

The fundamental configuration of a high-performance microprocessor for virtual memory systems is described, which was designed to TRON specifications[1]. This microprocessor has a pipeline configuration that is separated into register-to-register operations and load/store operations; this enables high performance to be achieved, together with the provision of high-speed on-chip resources such as stack cache and data cache. By separating into the register-to-register operation pipeline and the memory access pipeline, it is possible to execute register-to-register operations and memory access in parallel, and to reduce the number of instruction execution clocks. High performance has been additionally achieved by splitting the on-chip operand cache into stack data and other-than-stack data portions, which enables the cache for stack data to be operated as a virtual register.

Pipeline Structure of Matsushita 32-bit Microprocessor

We have been designing a virtual memory support model with performance of more than 6MIPS, which is one model of the Matsushita 32-bit microprocessor series based on TRON CPU specifications. In this paper, our approaches for high performance and virtual memory support (i.e., on-chip cache memory and address translation buffer implementation, pipeline structure, and speed-up of branch instructions) are introduced. It developed, through performance evaluations, that this model achieves 7-9MIPS at a 20MHz clock rate.