Takashi Unagami

Electrical Conductance Characteristics of Single‐Crystal Lead Iodide Grown in Gels

The formation of single‐crystal by a gel method and the electrical conductivity of these crystals are reported. In the high‐temperature region above 245°C, the conduction is intrinsic with an activation energy of 1.70 eV and is controlled by the motion of the interstitial positive ions. At lower temperatures, from 190 to 245°C, the conductivity is extrinsic with an activation energy of 0.63 eV and is controlled by the motion of the ions through ion vacant lattice points. The conductivity below 190°C is interpreted to be due to p‐type conduction and has an activation energy of 0.30 eV. In this region, the conduction is controlled by the motion of holes. It is clear that remarkable changes in the conductivity characteristics are caused by heat‐treatment. The conductivity of heat‐treated crystalline increases by more than one order of magnitude compared with an as‐grown sample in the hole conduction region where the activation energy is 0.30 eV. Acceptor levels created by diffused Na also show an increase in conductivity after heat‐treatment.

Silicon Thin Film with Columnar Structure Formed by RF Diode Sputtering

The morphology of amorphous silicon (a-Si) thin films prepared by rf diode sputtering was examined. The self-bias potential drops sharply with deceasing argon gas pressure below 30 mTorr and strongly influences the morphology of the sputtered a-Si films. In particular, a film deposited at a pressure of 20 mTorr has a very highly oriented columnar structure and each column has a dome-shaped top. The experimental results show that the self-bias potential is an important determinant of sputtered a-Si film microstructure.

Formation of high‐quality, magnetron‐sputtered Ta2O5 films by controlling the transition region at the Ta2O5/Si interface

Magnetron‐sputtered Ta2O5 films on Si are analyzed for their applications to semiconductor devices. It is clarified that the transition region formed at the Ta2O5/Si interface plays a significant role in determining electrical characteristics. This transition region formed during the initial stage of deposition consists of a mixture of Ta, Si, and O, and its thickness is in the range of 4 to 6 nm. The composition profile of this transition region and its thickness depend on two dominant factors: (1) oxygen partial pressure in the sputtering gas and (2) the surface oxide thickness on Si prior to deposition. Furthermore, it is initially indicated that 2.5‐nm‐thick surface oxide formed on Si prior to deposition produces a significant deterioration in leakage current. By reducing the surface oxide thickness to as low as 1.8 nm and adjusting the oxygen partial pressure, an optimum transition region is formed, which makes it possible to obtain high‐quality Ta2O5 films with high dielectric breakdown strength exc...

Study of ECR Hydrogen Plasma Treatment on Poly-Si Thin Film Transistors

In order to improve the characteristics of poly-Si thin film transistors (TFTs), hydrogen plasma treatment using electron cyclotron resonance plasma (ECR plasma treatment) has been studied. ECR plasma treatment has improved carrier mobility and the ON/OFF current ratio of poly-Si TFTs, which have been found to be greater than those using conventional hydrogen plasma treatment with radio frequency plasma. The improvement in the poly-Si TFTs characteristics is due to the reduction in the carrier trap density at the poly-Si grain boundary. Furthermore, the ECR plasma treatment improves leakage current.

Reactive Ion Etching of Tantalum Pentoxide

Etching experiments were performed using a parallel plate, RF reactive ion etching (RIE) system (ANELVA DEM-451M) with a 13.56 MHz RF power supply. The 250 mm diameter electrodes with cathode coupled configuration are separated by 89 mm. The wafers are mounted on the water-cooled cathode during etching. The following fluorocarbon gases were used as etch gases: CF/sub 4/, CF/sub 4//H/sub 2/ (partial pressure ratio of CF/sub 4//H/sub 2/ = 80/20) and CF/sub 4//O/sub 2/ (partial pressure ratio of CF/sub 4//O/sub 2/ = 95/5). The system pressure during etching was controlled to between 10 mTorr and 100 mTorr. Ta/sub 2/O/sub 5/ films were fabricated using an RF magnetron sputtering system. The Ta/sub 2/O/sub 5/ target, which was 10 cm in diameter and 5 mm thick, was used in the sputtering experiments. The sputtering gas consisted of mixtures of argon and oxygen (partial pressure ratio of Ar/O/sub 2/ = 80/20). The wafers were patterned using Shipley AZ 1350 positive photoresist. Thickness measurements were performed with a Taylor-Hobson surface profilimeter. Etch rates for Ta/sub 2/O/sub 5/, SiO/sub 2/, single-crystalline silicon ( oriented, p-type and 1.2 to 1.8 ohm-cm) and Shipley AZ 1350 positive photoresist, and individual etch rate ratios were studied.

Novel phenomenon of avalanche breakdown saturation with negative resistance in a bipolar transistor

A breakdown saturation phenomenon of negative resistance has been observed in a bipolar transistor. The collector current becomes saturated and reaches a critical current (I/sub CC/) after avalanche breakdown. At this critical current, a negative resistance appears. I/sub CC/ is determined by the thermal condition of the transistor, as obtained from pulse measurements and temperature dependence. For the multiplication factor (M), it is clear that there are two distinct regions: 1) low voltage (Region I) and 2) higher voltage (Region II). In Region I, the multiplication factor begins to increase with increasing applied voltage and is fixed almost constant for temperature, whereas in Region II, the multiplication factor decreases with increasing temperature. As a result, (/spl part/M//spl part/V)/sub T//spl sime/0 is realized at about 20 V and 124/spl deg/C, corresponding to the saturation of avalanche breakdown.

EL characteristics of a TFEL/TFT stacked structure display device driven by a HV-Si/spl middot/TFT circuit

TFEL/TFT stacked structure display devices were fabricated onto a quartz substrate. By using a HV-TFT circuit as the basis of a TFEL/TFT device, an EL device on the TFT circuit can be switched at a sufficiently low signal line voltage of V/sub s/=2-3 V. The maximum brightness of the TFEL/TFT device is 230 cd/m/sup 2/ and the ON/OFF brightness ratio is more than 90 between Vs=0 and Vs=4 V at a V/sub app/ frequency of 5 kHz and a voltage of 50. Evaluation of the dynamic behavior of TFT circuits using multichannel HV-Si/spl middot/TFTs showed that the rise time of the fundamental TFT circuit at the EL driving point of the circuit was about 20 /spl mu/s and that the hold time of the circuit was about 70 mS. The rise time and the fall time of the luminescence were each about 20 /spl mu/s. The memory characteristics of the TFEL/TFT device showed that the hold time of the luminescence was about 40 mS. These dynamic characteristics of the TFEL/TFT stacked structure device satisfy the conditions required for a flat panel display.

Study on Narrow-Stripe Polycrystalline Silicon Thin-Film Transistors

N-channel thin-film transistors which have narrow channel stripes (narrow-stripe TFTs) have been proposed to improve the characteristics of poly-Si TFTs. The carrier mobility of narrow-stripe TFTs is larger than that of conventional structure TFTs. It is found that the mobility increase is due to the reduction of the potential-barrier height at the poly-Si grain boundary and the potential-barrier height decreases with decreasing channel stripe width. Furthermore, after hydrogen-plasma treatment, the carrier mobility in narrow-stripe TFTs with 0.9?m wide stripes becomes 7.4 cm2/(V?s) which is more than three times that of conventional TFTs.

Effects of ECR Hydrogen-Plasma Treatment on Narrow-Stripe Polycrystalline Silicon Thin-Film Transistors

The characteristics of thin-film transistors (TFTs) have been examined to determine the effects of a narrow-stripe structure of polycrystalline silicon in the channel region and of a hydrogen-plasma treatment utilizing electron cyclotron resonance (ECR hydrogen-plasma treatment). After this treatment, the carrier mobility, even for small-grain poly-Si, achieves 11.3 cm2/(Vs) for the narrow-stripe TFT. This high carrier mobility can be obtained according to the remarkable reduction of the potential barrier height of poly Si, which is attained by making poly-Si narrow and by ECR hydrogen-plasma treatment.

Observation of a Sharp Notch at a Si-PN Junction Formed by Anodization in HF Solution

Porous silicon was prepared in a square p + -Si ring formed in an N-type Si epitaxial layer grown on a p-type Si substrate. A sharp notch was generated at the PN junction of the surface during anodization in HF solution. The notch formed at the boundary between the porous silicon region and the N-type silicon region. The notch began to appear at the outside P + ring. It also appeared at the inside p + ring during anodization. This notch had a V shape with a steep slope at the N-type silicon side which grows with anodization time. Using the Si 3 N 4 film mask method, the generation of the notch could be prevented. The notch at the PN junction was considered to be formed due to Si etching caused by localized electropolishing near the PN junction.