Takashige Baba

A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking

This paper describes a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Although minimizing the circuit area has become critical in multibit interfaces such as the SFI-5, few studies have proposed a practical method of reducing the area of data recovery circuits. We introduce a digital-PLL-type DR circuit design with eye-tracking, which we developed to minimize the circuit area and power consumption without degrading tolerance against jitter. This novel method of data recovery enabled us to simplify the circuit design against process, voltage, and temperature variations. Design considerations on how to eliminate high-frequency jitter and how to track long-term wander are described. The design for 2.5-GHz clock distribution is also discussed. The area of the DR circuit, fabricated with 0.18-/spl mu/m SiGe BiCMOS technology, is 0.02 mm/sup 2//ch, and its power consumption is 50 mW/ch at 1.8 V. The measured tolerance against jitter at 2.5 Gb/s is 0.7 UI peak-to-peak, which satisfies the jitter specifications for the SFI-5.