Takatoshi Igarashi

Evaluation of plasma process damage during TSV formation and damage reduction method

In this study, the impact of plasma stress during TSV (Through Silicon Via) formation process on the device characteristics is investigated. In the TSV formation process, there are several plasma assisted processes such as etching, metal/insulator deposition, ashing and so on, and the devices are exposed to the ambient plasma during these processes. To evaluate the plasma damage, we prepared TEG (Test Element Group) wafers which contain two types of MOSFET; P-Channel MOS and N-Channel MOS, and the TEG wafers include the variation of the gate length and the gate width. We performed TSV process on the TEG wafers including support wafer bonding, TSV wet etching, insulator formation, insulator etching, backside metal formation and passivation formation. After the TSV formation processes, significant threshold voltage shift ΔVth was observed in both types of MOSFET. By conducting additional annealing process, the amount of Vth shift decreased, which implies that the Vth shift occurred because of the defects in the gate oxide induced by the trapped charges in the gate electrode. We also attempted a damage reduction method. In this process, the electrode pads of MOSFET (gate, source, drain and substrate) of each device were electrically connected during the TSV process. After the TSV process, no Vth shift was observed because plasma charges can disperse into the substrate through the connected metal line.

Wafer level package by using post dicing process

This paper describes the new wafer level packaging process with the diced chip array on the small-diameter handling wafer. The general purpose of wafer level packaging is to realize a smaller, more functional and cost effective electronic package. For example, Wafer Level chip size package and Wafer stacking 3D package are the most effective packaging processes/structures using semiconductor wafer process. In the semiconductor industrial trend, silicon wafer sizes become larger to achieve a higher chip throughput and to reduce a chip cost. However in actual applications, the packaging needs are diversified and the required number of each package type does not meet the huge sized wafer processing. In this paper, we introduce the new packaging technique. In this new technique, after dicing CMOS wafer to the individual chips, we rearrange them on another smaller handling wafer. We, then, planarize the surface after filling up the resin on it, which can be used just like a single wafer. As the result, we can have a free hand to choose the size of handling wafer, and it means that we can use the existing equipment, which leads to lower cost and shorter development time. First, the influence of residual stress after rearranging the matrix of chip on the handling wafer was investigated with using FEM-modeling. It was found that the both of the sell size of the matrix and the material properties of the filled resin greatly influence on the wafer warpage, and that the design of matrix and the material of resin are key to complete the process of this new technique. Second, we tried to apply this new technique to an image sensor. 8×8 matrix of 9mm2 CMOS image sensor chips are rearranged on 4inch glass wafer, and we fabricated TSVs in the image sensor chips for chip size package.

Influence of surface properties on adhesion strength of dielectric passivation in chip size packaging

This study focuses on adhesion strength of the dielectric passivation for RDL (Redistribution Layer) process in CSP (Chip Size Packaging). The relationship between the surface state and the adhesion of the dielectric passivation was investigated. Dielectric passivation is a layer for protecting the wiring, and adhesion to the base substrate surface and the wiring material surface is important. To improve the adhesion strength, it is necessary to grasp factors that affect the adhesion strength. Surface properties of substrates such as mechanical and chemical properties were investigated before and after the dielectric passivation forming process. In the case of using the organic dielectric passivation, it was revealed that metal and fluorine residues after RDL formation were the main factor to weaken the adhesion strength. To remove these residues, argon plasma treatment was found to be effective. In addition, adhesion strength was also improved. The CSP applied with argon plasma treatment passed the reliability test. It was thought that the improvement of adhesion strength might make large contribution to it.