Takaya Kitahara

Full RF module with embedded filters for 2.4 GHz and 5 GHz dual band WLAN applications

Small size radio frequency (RF) multi chip module for dual band (2.4 GHz and 5 GHz) wireless local area network (WLAN) applications is described. The full functions between base band input/output (I/O) and RF antenna switch are integrated in the RF module. In order to reduce size of the RF module, embedded 5 GHz band pass filter (BPF), build-up multi-layer organic substrate and flip chip technology are used. Size of the RF module is 24 mm/spl times/32 mm/spl times/2.1 mm, including shield cover and connectors. This is the minimum size in modules with same functions for dual band WLAN as far as the authors know. And electrical performances of the RF module are evaluated using WLAN signals. This report presents design and experimental results of small size RF module for dual band WLAN applications.

RF module using MCM-L and BGA technology for 5 GHz WLAN application

This paper presents the design concept and experimental results about small size radio frequency (RF) module for 5GHz wireless local area network (WLAN). Functions of the RF module include from base band input/output to antenna switch. The size is 20mm × 15mm × 3mm and that is minimum size in modules with same functions as far as the authors get to know. For the purpose of small size and low cost, generally known technologies are used. They are multi chip module on laminated-base dielectric substrate (MCM-L) technology, interconnection of each layer using build-up technology, flip chip technology and ball grid array (BGA) technology. Parts and ICs are on both sides of the RF modules substrate and are vertically connected in the substrate. In order to ensure electrical performance at 5GHz frequency band in the high-density package, transmission line characteristics in the substrate and BGA characteristic are simulated by 3 dimensional (3D) electromagnetic (EM) software. The fabricated RF module is evaluated using the test set up for 5GHz WLAN application and the result is shown.

Asymmetrical Doherty amplifier using GaN HEMTs for high-power applications

In this paper, we present an asymmetrical Doherty amplifier (DA) that can enhance the efficiency at a 9.5 dB backoff from its saturated output power (PSAT). The asymmetrical DA consists of a peak amplifier and a carrier amplifier with two and one 210 W gallium nitride (GaN) high-electron-mobility transistors (HEMTs), respectively. A Wilkinson combiner at the output of the peak amplifier enables the stable operation of the GaN HEMTs for high-power applications. The asymmetrical DA is designed and fabricated for the ultrahigh-frequency (UHF) band. Measurement results using a continuous wave (CW) signal indicate a drain efficiency (ηd) of 60% at a PSAT of 57.5 dBm and a ηd of 56% at a 9.5 dB backoff from PSAT. For a 6 MHz orthogonal frequency-division multiplexing (OFDM) signal with a high peak-to-average power ratio (PAPR), the measurement results indicate a ηd of 52% and an adjacent-channel leakage power ratio (ACLR) of -41 dBc at an average output power (PAVE) of 48 dBm using a digital predistorter. To the best of our knowledge, this is the highest ηd and output power for an OFDM signal.

Doherty power amplifier with asymmetrical drain voltages for enhanced efficiency at 8 dB backed-off output power

In this paper, we present a high-efficiency 300 W Doherty power amplifier (DPA) that can improve the efficiency at an 8 dB backoff from its saturated output power (PSAT). To enhance the efficiency, asymmetrical drain voltages are supplied to a carrier amplifier and a peak amplifier in the DPA. The drain voltages and radio frequency (RF) circuit parameters of each amplifier are determined by basic load-impedance analysis. The DPA is fabricated using a push-pull laterally diffused metal oxide semiconductor (LDMOS) field-effect transistor (FET) for an ultrahigh frequency (UHF) band. The drain voltages are set to 50 V and 30 V. Measurement results using a continuous wave (CW) signal indicate a drain efficiency (ηd) of 50% at a PSAT of 55 dBm and a ηd of 48% at an 8 dB backoff from PSAT, which means that the proposed DPA can extend the power range in which its highest efficiency is maintained. For a wideband code division multiple access (W-CDMA) signal with a peak-to-average power ratio (PAPR) of 8 dB, the measurement results indicate a ηd of 43% and an adjacent-channel leakage power ratio (ACLR) of −23 dBc at an output power of 47 dBm.

RF Design of On-Chip EMI Filters in CMOS Logic IC

In this paper, we present new design methods that provide the radio frequency (RF) rejection performance of on-chip electromagnetic interference (EMI) filters in a complementary metal-oxide semiconductor (CMOS) logic integrated circuit (IC). In order to simulate on-chip performance, we consider the following concepts. Firstly, simulation models consist of simulation program with integrated circuit emphasis (SPICE) models of logic circuits, an IC chip design, an IC package design and a printed circuit board (PCB) design. Secondly, RF rejection performance is obtained using a frequency domain analysis of output data signals from ICs including and excluding EMI filters. Simulation results show that an on-chip-type EMI filter has better performance in the frequency band for wireless communications than other types of EMI filter. The measurement results show good agreement with the simulation results.