Takayuki Ikeda

RFCPUs on glass and plastic substrates fabricated by TFT transfer technology

On the basis of the fabrication of a CPU on glass as a digital circuit presented in B. Lee et al. (2003) and T. Ikeda et al. (2004), as well as the fabrication of a flexible CPU using a TFT transfer technology presented in T. Takayama et al. (2004), we have succeeded in the development of the worlds first flexible RFCPUs (8bit, passive type) by adding to the CPU an antenna, an analog circuit, an encryption function and an RFID function, which operate using an RF signal with a frequency of 13.56MHz

30.9 Normally-off computing with crystalline InGaZnO-based FPGA

An FPGA employing c-axis aligned crystal In-Ga-Zn oxide (CAAC-IGZO) FET [1] based configuration memories (CMs) is known to need no reconfiguration thanks to nonvolatile CMs, shows high operation speed due to boosting effect of pass gates used in routing switches (RS) [2], and easily realizes fine-grained multi-context (FG-MC) architecture [2] because CMs which need very low power to keep the contents can be constructed with a small number of transistors. It would be very difficult to realize all of these features in FPGAs using MRAM [3] or RRAM [4]. These features are very unique to the CAAC-IGZO FPGA.

Crystalline In?Ga?Zn?O FET-based configuration memory for multi-context field-programmable gate array realizing fine-grained power gating

A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 ?m c-axis aligned crystalline In?Ga?Zn?O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 ?m complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 ?s at 2.5 V and 10 MHz driving.

A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology

A boosting pass gate (BPG) suitable for a programmable routing switch including a c-axis aligned crystal In-Ga-Zn-O (CAAC-IGZO) field effect transistor (FET) is proposed. The CAAC-IGZO is one of crystalline oxide semiconductors (OS). The proposed BPG (OS-based BPG, OS BPG) has a combination of a pass gate (PG) and a configuration memory (CM) cell utilizing a CAAC-IGZO FET with extremely low OFF-state current and a storage capacitor. This OS BPG achieves a routing switch with fewer transistors than a conventional routing switch having a combination of a PG and an static RAM (SRAM) cell. Owing to the boosting effect, the switching characteristics, at not only positive transition but also negative transition of input signals, of the OS BPG are improved without using overdriving. In circuits fabricated with a hybrid process of a CMOSFET and a CAAC-IGZO FET with gate lengths of 0.5 and 1.0 μm, the net delays of the OS BPG, 75 and 58 ns, at driving voltages of 2.0 and 2.5 V have been found to be less than those of the conventional routing switch (SRAM-based PG, SRAM PG) by about 79% and 62%, respectively. It has also been confirmed that a field-programmable gate array (FPGA) chip utilizing the OS BPG as a routing switch reduces the layout areas of routing switches and the whole chip by 61% and 22%, respectively, and increases the maximum operating frequencies at driving voltage of 2.0 and 2.5 V by about 2.8 times and 1.6 times of those of the FPGA chip utilizing the SRAM PG as a routing switch.

Applications of crystalline Indium-Gallium-Zinc-Oxide technology to LSI: Memory, processor, image sensor, and field programmable gate array

Crystalline In-Ga-Zn Oxide (IGZO) including c-axis aligned crystal (CAAC) enables FETs to show high reliability and extremely low off-state current. CAAC-IGZO technology is expected to grow to main technology of next-generation displays and is already contributing to mass-production of liquid crystal displays. In this paper by focusing on a very important feature of CAAC-IGZO FET, extremely low off-state current, its pioneering various applications to LSI are reviewed and discussed. In particular, a success in development of a hybrid process of CMOS FETs and CAAC-IGZO FETs promotes our developments of novel memories, processors, image sensors, and recently, field programmable gate arrays (FPGA).

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

A radio frequency integrated circuit (RFIC) tag consisting of an 8 bit CPU, a 4 kB ROM, a 512B SRAM, and an RF circuit, which communicates using 915 MHz UHF RF signals, has been developed on both a flexible substrate and a glass substrate. Each of the RFIC tags employs a single DES and an anti-side channel attack routine in firmware for secured communication, and occupies an area of 10.5 mm in width and 8.9 mm in height. The RFIC tag on the flexible substrate is 145 mum thick and weighs 262 mg, and the RFIC tag on the glass substrate consumes 0.54 mW at a power supply voltage of 1.5 V and communicates with a maximum range of 43 cm at a power of 30 dBm. The high-performance poly-silicon TFT technology on flexible substrate and glass substrate of 0.8 mum design rule, and a gate plus one metal layer are used for fabrication. The RFIC tag realizes stable internal clock generation and distribution by a digital control clock generator and a two-phase nonoverlap clock scheme, respectively.

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 μm crystalline oxide semiconductor FET on a 0.5 μm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.

6.5 25.3μW at 60fps 240×160-pixel vision sensor for motion capturing with in-pixel non-volatile analog memory using crystalline oxide semiconductor FET

A vision sensor used to capture motion must operate with very low power when used in sensor networks where power is very limited. Frame-based [1] and event-driven [2,3] vision sensors have been reported. The former captures motion from the difference between captured data of a previous frame and that of a current frame; thus, it is difficult to capture motion of a slowly moving object. An event-driven sensor captures motion of a slowly moving object; however, its pixel configuration is complicated, and it is difficult to perform both motion capturing and image capturing. In this paper, we report a vision sensor for motion capturing having in-pixel non-volatile analog memory utilizing a c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO), a crystalline oxide semiconductor based FET that demonstrates very low off-state current [4] and retains captured data of a given reference frame. Although an electronic global shutter image sensor with improved floating diffusion (FD) charge retention characteristics is reported in [5], our vision sensor realizes normal global shutter and motion capturing depending on the presence or absence of differences with respect to a given reference frame in each pixel. The sensor has 3 modes: an imaging mode to output captured data in pixels, a motion-capturing mode to process differential data using an analog processor, and a standby mode to reduce power after motion capturing for each frame. Power consumption is reduced by operating only circuit blocks needed for each mode. The sensor (240×160 pixels), fabricated by a 0.5μm CAAC-IGZO FET/0.18μm p-channel Si FET (no n-channel Si FET) hybrid process shows power consumption of 25.3μW and 1.88μW at 60fps in the motion-capturing and standby modes, respectively, which equal 1/140th and 1/2000th of the power consumption of the imaging mode.

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) has been developed, which is capable of subthreshold operation used for energy harvesting. To achieve subthreshold operation, the CAAC-IGZO FPGA has a structure designed as an extension of a boosting pass gate using a CAAC-IGZO FET and employs overdriving of a programmable routing switch and a programmable power switch for power gating (PG). A CAAC-IGZO FET is used to give an ideal floating gate with excellent charge retention. A chip fabricated using a 0.8-μm CAAC-IGZO/0.18-μm CMOS hybrid process achieves subthreshold operation while maintaining the features required for normally off computing proposed in our previous study. Specifically, these features are realized by fine-grained PG for individual programmable logic elements (PLEs), fast configuration switching between contexts, and load/store between a volatile register and a nonvolatile shadow register in the PLEs. The chip operation at a minimum operating voltage of 180 mV with a combinational circuit configuration is demonstrated. With a sequential circuit configuration, the chip operates at a minimum operating voltage of 190 mV with 12.5 kHz, and the minimum power-delay product is 3.40 pJ/operation at 330 mV.

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Utilizing a c-axis-aligned crystalline oxide semiconductor-based FET, we have fabricated a vision sensor with in-pixel nonvolatile analog memory. The sensor realized normal image data capturing, captured differential data of a given reference frame, and retained the captured data for an extended time in each pixel. Moreover, the sensor realized normal global shutter image capturing and motion capturing by extracting differential images. This is performed using the captured data and depends on the presence or absence of differences between normal images and reference images. The sensor has three operating modes: an imaging mode, a motion capturing mode, and a wait mode. Importantly, power consumption is reduced by powering off circuit blocks that are in a standby state.