Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Takehide Shirato is active.

Publication


Featured researches published by Takehide Shirato.


custom integrated circuits conference | 1988

A 120 K-gate usable CMOS sea of gates packing 1.3 M transistors

Yoshiyuki Suehiro; Daisuke Miura; Mitsugu Naitoh; Sadao Tsutsumi; Takehide Shirato

A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with high density and suitable routing areas for random logic circuits, and results in the utilization of 120 K basic cells. It is fabricated with CMOS 1.0- mu m triple-metal-layer process technology.<<ETX>>


Archive | 1986

Semiconductor device having a silicon on insulator structure

Takehide Shirato; Nobuhiko Aneha


Archive | 1983

Method of forming conductive channel extensions to active device regions in CMOS device

Takehide Shirato


Archive | 1985

Protection device in an integrated circuit

Takehide Shirato; Shinichi Sekine


Archive | 1986

Method for fabricating an insulated-gate FET having a narrow channel width

Takehide Shirato; Taiji Ema


Archive | 1986

Semiconductor device having a protection circuit with lateral bipolar transistor

Takehide Shirato


Archive | 1985

A complementary semiconductor device having high switching speed and latchup-free capability

Takehide Shirato


Archive | 1983

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH OUTPUT STAGE

Takehide Shirato; Touru Inaba


Archive | 1981

Mask ROM-type semiconductor memory device

Takehide Shirato


Archive | 1989

Semiconductor device having a high breakdown voltage characteristic

Takehide Shirato

Collaboration


Dive into the Takehide Shirato's collaboration.

Researchain Logo
Decentralizing Knowledge