Takeshi Ikenaga

Content Based Hierarchical Fast Coding Unit Decision Algorithm for HEVC

Large coding unit which is also known as super macroblock, has already been adopted in the test model of next generation coding standard called high efficiency video coding. The coding unit which is larger than 16x16 and less than or equal to 64x64 provides great bit rate saving while the coding complexity increases dramatically. In this paper, we propose a fast coding unit decision algorithm in either frame level or coding unit level to accelerate encoding procedure. In frame level, by analyzing the utilization rate of coding unit in all depth, we skip several rarely used coding units in specified depth. In coding unit level, the neighbor and co-located coding unit information are referred for further skipping coding unit in unnecessary depth. Results show our proposed algorithm provides averagely 45% total encoding time reduction and negligible drop of rate distortion performance.

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit media embedded processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb system-in-silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 mum CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 mm2 die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

A Contour-Based Robust Algorithm for Text Detection in Color Images

Text detection in color images has become an active research area in the past few decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. The proposed algorithm is based on the combination of connected component and texture feature analysis of unknown text region contours. First, we utilize an elaborate color image edge detection algorithm to extract all possible text edge pixels. Connected component analysis is performed on these edge pixels to detect the external contour and possible internal contours of potential text regions. The gradient and geometrical characteristics of each region contour are carefully examined to construct candidate text regions and classify part non-text regions. Then each candidate text region is verified with texture features derived from wavelet domain. Finally, the Expectation maximization algorithm is introduced to binarize each text region to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness of texture based analysis. Experimental results show that our proposed algorithm is robust in text detection with respect to different character size, orientation, color and language and can provide reliable text binarization result.

High performance VLSI architecture of fractional motion estimation in H.264 for HDTV

Fractional motion estimation (FME) on sub-pixels will occupy almost over 45% of the computation complexity of H.264 encoding process. Therefore a high performance VLSI architecture of FME is described in this paper to achieve the capacity of encoding the high-resolution real-time video stream for HDTV. Our design is improved from an existing work by involving a pipeline strategy in sub-pixel interpolation unit which can avoid the long delay paths in 6-tap ID FIR so as to increase the clock frequency up to 200MHz. Moreover, a 16-pixel search engine is adopted to remove the redundant interpolation area and parallelize the various block size search which can save more than half of the clock cycles in processing a macro block. Our design is implemented with only 189K gates at operating frequency of 200MHz in worst case (285MHz in typical case). It can provide the processing capacity of more than 250K MB/sec which is enough for 1080HD (1920times1088) video streams at frame rate of 30fps. It is a useful intellectual property (IP) design for multimedia system

A fully-parallel 1 Mb CAM LSI for real-time pixel-parallel image processing

For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM), or an associative processor, that can perform various types of parallel processing with words as the basic unit is a promising component for creating such a system because of its suitability for LSI implementation. Conventional CAM LSIs, however, have neither efficient function nor enough capacity for pixel-parallel processing. This paper describes a fully parallel 1-Mb CAM LSI. It has advanced functions for processing various pixel-parallel algorithms, such as mathematical morphology and discrete-time cellular neural networks. Moreover, since it has 16-K words, or processing elements (PEs), which can process 128/spl times/128 pixels in parallel, a board-sized pixel-parallel image-processing system can be implemented using several chips. A chip capable of operating at 56 MHz and 2.5 V was fabricated using 0.25-/spl mu/m full-custom CMOS technology with five aluminum layers. A total of 15.5 million transistors have been integrated into a 16.1/spl times/17.0 mm chip. Typical power dissipation is 0.25 W. Processing performance of various update and data transfer operations is 3-640 GOPS. This CAM LSI will make a significant contribution to the development of compact, high-performance image-processing systems.

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the tuning when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

A 1.41W H.264/AVC Real-Time Encoder SOC for HDTV1080P

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5 Gbps 64 Mb system-in-silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 m CMOS technology, the SoC core occupies 27.1 mm die area and consumes 1.41 W at 200MHz in typical work conditions.

Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation

Intra coding algorithm in High Efficiency Video Coding employs up to 35 directional prediction modes. Upon the end of alleviating the intra encoding complexity, we proposed the candidate mode selection algorithm from analyzing the textures of the source image block. Considering the fine difference between the neighboring prediction directions, we devise the fix-point arithmetic based edge detector, which improves the direction detection accuracy as compared with the typical previous works while maintaining the low computational overhead. To improve the robustness of the edge direction statistics, we further introduce the conception of kernel density estimation into the histogram calculation. Our proposals is orthogonal to the published HEVC fast intra mode decision algorithms. Experimental results verified that, on average, the proposed methods reduced the encoding time by 25.21% in high efficiency mode, and 37.61% in low complexity mode, whereas the averaging BDPSNR losses are 0.0608dB and 0.0781dB, respectively. 1.

A robust algorithm for text detection in color images

Text detection in color images has become an active research area since recent decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. First, we use an elaborate edge detection algorithm to extract all possible text edge pixels. Second connected component analysis is employed to construct text candidate region and classify part non-text regions. Third each text candidate region is verified with texture features derived from wavelet domain. Finally, the expectation maximization algorithm is introduced to binarize text regions to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness of texture based analysis. Experimental results show that our algorithm is robust in text detection with respect to different character size, orientation, color and language and can provide reliable text binarization result.

A Highly Parallel Architecture for Deblocking Filter in H.264/AVC

This paper presents a highly parallel architecture for deblocking filter in H.264/AVC. We adopt various parallel schemes in memory sub-system and datapath. A 2-dimensional parallel memory scheme is employed to support efficient parallel access in both horizontal and vertical directions in order to speed up the whole filtering process. This parallel memory also eliminates the need for a transpose circuit. In the datapath, an algorithm optimization is performed to implement parallel filtering with hardware reuse. Pipeline techniques are also adopted to improve the throughput of filtering operations. Our design is implemented under TSMC 0.18 μm technology. Results show that the core size is 0.82 × 1.13 mm2 when the maximum frequency is 230 MHz. Compared to other existing architectures, our design has advantages in both speed and area.